Page 1 SC32442B54 USER’S MANUAL Revision 1.0...
Page 2: Product Overview
PRODUCT OVERVIEW INTRODUCTION This user’s manual describes SAMSUNG's SC32442B 16/32-bit RISC microprocessor. SAMSUNG’s SC32442B is designed to provide hand-held devices and general applications with low-power, and high-performance micro- controller solution in small die size. To reduce total system cost, the SC32442B includes the following components.
Page 3 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR FEATURES • Architecture 4KB internal buffer for booting. • • Integrated system for hand-held devices and Supports storage memory for NAND flash general embedded applications. memory after booting. • • 16/32-Bit RISC architecture and powerful Supports Advanced NAND flash instruction set with ARM920T CPU core.
Page 4 Dead-zone generation mode • Supports external clock sources • LPC3600 Timing controller embedded for LTS350Q1-PD1/2(SAMSUNG 3.5” Portrait / RTC (Real Time Clock) 256K-color/ Reflective a-Si TFT LCD) • Full clock feature: msec, second, minute, hour, • LCC3600 Timing controller embedded for date, day, month, and year LTS350Q1-PE1/2(SAMSUNG 3.5”...
Page 5 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR FEATURES (Continued) • A/D Converter & Touch Screen Interface Compatible with SD Memory Card Protocol version 1.0 • 8-ch multiplexed ADC • Compatible with SDIO Card Protocol version 1.0 • Max. 500KSPS and 10-bit Resolution •...
Page 6 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW BLOCK DIAGRAM ARM920T IPA[31:0] Instruction External Instruction CACHE Coproc (16KB) Interface IVA[31:0] ID[31:0] ARM9TDMI AMBA JTAG Processor core CP15 (Internal Embedded ICE) DD[31:0] Write Buffer DVA[31:0] DVA[31:0] Data WriteBack WBPA[31:0] Data CACHE PA Tag (16KB) DPA[31:0] BUS CONT.
Page 7: Pin Assignments
PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR PIN ASSIGNMENTS 14mm(H)x14mm(V)x1.6mm(T) TOP VIEW Figure 1-2. SC32442B Pin Assignments (332-FBGA)
Page 8 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1. 332-Pin FBGA Pin Assignments – Pin Number Order (Sheet 1 of 4) Pin Name Pin Name Pin Name Number Number Number ADDR10 ADDR1 VDDI ADDR13 ADDR12 VSSCOM NGCS5/GPA16 ADDR15 ADDR16/GPA1 NBE1 ADDR23/GPA8 VDDI NSRAS ADDR18/GPA3 VDDMOP...
Page 9 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-1. 332-Pin FBGA Pin Assignments – Pin Number Order (Sheet 2 of 4) Pin Name Pin Name Pin Name Number Number Number SCLK0 TOUT0/GPB0 VSSCOM VDDMOP CAMDATA6/GPJ6 VSSCOM NFCE/GPA22 TXD2/NRTS1/GPH6 VDDOP1 CAMDATA5/GPJ5 TXD0/GPH2 VSSA_UPLL VSSMOP XTIPLL RXD1/GPH5...
Page 10 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1. 332-Pin FBGA Pin Assignments – Pin Number Order (Sheet 3 of 4) Pin Name Pin Name Pin Name Number Number Number VLINE/GPC2 AA15 SPIMISO0/GPE11 AC25 AIN3 VD4/GPC12 AA16 SPICLK0/GPE13 AC26 VCC_NF EINT15/SPICLK1/GPG7 AA17 DN1/PDN0 VSS_SDRAM AIN6...
Page 11 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-1. 332-Pin FBGA Pin Assignments – Pin Number Order (Sheet 4 of 4) Pin Name Pin Name Number Number VD20/GPD12 VD21/GPD13 VSSQ_SDRAM VDDQ_SDRAM AF26 CDCLK/GPE2 VSSQ_SDRAM AF10 VDDQ_SDRAM AF11 VSS_SDRAM AF12 VSSQ_SDRAM AF13 VDD_SDRAM AF14 EINT11/NSS1/GPG3 AF15...
Page 12 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-2. SC32442B 332-Pin FBGA Pin Assignments (Sheet 1 of 10) Default I/O State I/O State I/O State I/O Type Number Name Function @BUS REQ @Sleep @nRESET t12s ADDR0/GPA0 ADDR0 Hi-z/– O(L)/– O(L) t12s ADDR1 ADDR1 Hi-z O(L)
Page 13 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-2. SC32442B 332-Pin FBGA Pin Assignments (Sheet 2 of 10) Default I/O State I/O State I/O State I/O Type Number Name Function @BUS REQ @Sleep @nRESET AB25 XP/AIN7 –/– –/– CAMDATA0/GPJ0 GPJ0 –/– Hi-z/– CAMDATA1/GPJ1 GPJ1 –/–...
Page 14 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-2. SC32442B 332-Pin FBGA Pin Assignments (Sheet 3 of 10) Default I/O State I/O State I/O State I/O Type Number Name Function @BUS REQ @Sleep @nRESET DATA19 DATA19 Hi-z Hi-z,O(L) b12s DATA20 DATA20 Hi-z Hi-z,O(L) b12s DATA21...
Page 15 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-2. SC32442B 332-Pin FBGA Pin Assignments (Sheet 4 of 10) Default I/O State I/O State I/O State I/O Type Number Name Function @BUS REQ @Sleep @nRESET AB20 EINT16/GPG8 GPG8 –/– Hi-z/– AB21 EINT17/nRTS1/GPG9 GPG9 –/–/–...
Page 16 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-2. SC32442B 332-Pin FBGA Pin Assignments (Sheet 5 of 10) Default I/O State I/O State I/O State I/O Type Number Name Function @BUS REQ @Sleep @nRESET t12s nGCS7 nGCS7 Hi-z Hi-z,O(H) O(H) t12s nSCAS nSCAS Hi-z Hi-z,O(H)
Page 17 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-2. SC32442B 332-Pin FBGA Pin Assignments (Sheet 6 of 10) Default I/O State I/O State I/O State I/O Type Number Name Function @BUS REQ @Sleep @nRESET SCKE SCKE Hi-z O(L) O(H) t12s SCLK0 SCLK0 Hi-z O(L) O(SCLK)
Page 18 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-2. SC32442B 332-Pin FBGA Pin Assignments (Sheet 7 of 10) Default I/O State I/O State I/O State I/O Type Number Name Function @BUS REQ @Sleep @nRESET VD2/GPC10 GPC10 –/– O(L)/– VD3/GPC11 GPC11 –/– O(L)/– VD4/GPC12 GPC12 –/–...
Page 19 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-2. SC32442B 332-Pin FBGA Pin Assignments (Sheet 8 of 10) Default I/O State I/O State I/O State I/O Type Number Name Function @BUS REQ @Sleep @nRESET AA20 VDDi VDDi d12c VDDi VDDi d12c VDDi VDDi d12c VDDi...
Page 20 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-2. SC32442B 332-Pin FBGA Pin Assignments (Sheet 9 of 10) Default I/O State I/O State I/O State I/O Type Number Name Function @BUS REQ @Sleep @nRESET VDDQ_SDRAM VDDQ_SDRAM VDDQ_SDRAM VDDQ_SDRAM AF10 VDDQ_SDRAM VDDQ_SDRAM AF15 VDDQ_SDRAM VDDQ_SDRAM AF19...
Page 21 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-2. SC32442B 332-Pin FBGA Pin Assignments (Sheet 10 of 10) Default I/O State I/O State I/O State I/O Type Number Name Function @BUS REQ @Sleep @nRESET VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP...
Page 22 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW NOTE: 1. The @BUS REQ. shows the pin state at the external bus, which is used by the other bus master. 2. ' – ‘ mark indicates the unchanged pin state at Bus Request mode. 3.
Page 23 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR THE TABLE BELOW SHOWS I/O TYPES AND DESCRIPTIONS. Input (I)/Output (O) Type Descriptions d12i(vdd12ih_45p) 1.2V Vdd for alive power 1.2V Vdd/Vss for internal logic d12c(vdd12ih_core_45p), si(vssiph_45p) d18o(vdd18op_ddr), s18(vsso_ddr) 1.8V Vdd/Vss for external logic 33o(vdd33oph), so(vssoph) 3.3V Vdd/Vss for external logic d33th(vdd33th_abb),sth(vssbbh_abb) 3.3V Vdd/Vss for analog circuitry...
Page 24 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW SIGNAL DESCRIPTIONS Table 1-3. SC32442B Signal Descriptions (Sheet 1 of 6) Signal Input/Output Descriptions Bus Controller OM[1:0] OM[1:0] sets SC32442B in the TEST mode, which is used only at fabrication. Also, it determines the bus width of nGCS0. The pull-up/down resistor determines the logic level during RESET cycle.
Page 25 TFT: Data enable signal LEND TFT: Line End signal SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal LCD_HCLK SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal...
Page 26 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-3. SC32442B Signal Descriptions (Sheet 3 of 6) Signal Input/Output Descriptions UART RxD[2:0] UART receives data input TxD[2:0] UART transmits data output nCTS[1:0] UART clear to send input signal nRTS[1:0] UART request to send output signal UEXTCLK External clock input for UART AIN[7:0]...
Page 27 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-3. SC32442B Signal Descriptions (Sheet 4 of 6) Signal Input/Output Description SPIMISO[1:0] SPIMISO is the master data input line, when SPI is configured as a master. When SPI is configured as a slave, these pins reverse its role. SPIMOSI[1:0] SPIMOSI is the master data output line, when SPI is configured as a master.
Page 28 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-3. SC32442B Signal Descriptions (Sheet 5 of 6) Signal Input/Output Description Reset, Clock & Power XTOpll Crystal Output for internal osc circuit. When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source.
Page 29 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-3. SC32442B Signal Descriptions (Sheet 6 of 6) Signal Input/Output Description Power VDDALIVE SC32442B reset block and port status register VDD. It should be always supplied whether in normal mode or in Sleep mode. VDDIARM SC32442B core logic VDD for ARM core.
Page 30 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW SC32442B SPECIAL REGISTERS Table 1-4. SC32442B Special Registers (Sheet 1 of 14) Register Address Address Acc. Read/ Function Name (B. Endian) (L. Endian) Unit Write Memory Controller ← BWSCON 0x48000000 Bus Width & Wait Status Control BANKCON0 0x48000004 Boot ROM Control...
Page 31 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-4. SC32442B Special Registers (Sheet 2 of 14) Register Name Address Address Acc. Read/ Function (B. Endian) (L. Endian) Unit Write USB Host Controller ← HcRevision 0x49000000 Control and Status Group HcControl 0x49000004 HcCommonStatus 0x49000008 HcInterruptStatus 0x4900000C...
Page 32 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. SC32442B Special Registers (Sheet 3 of 14) Register Address Address Acc. Read/ Function Name (B. Endian) (L. Endian) Unit Write ← DISRC0 0x4B000000 DMA 0 Initial Source DISRCC0 0x4B000004 DMA 0 Initial Source Control DIDST0 0x4B000008 DMA 0 Initial Destination...
Page 33 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-4. SC32442B Special Registers (Sheet 4 of 14) Register Address Address Acc. Read/ Function Name (B. Endian) (L. Endian) Unit Write Clock & Power Management ← LOCKTIME 0x4C000000 PLL Lock Time Counter MPLLCON 0x4C000004 MPLL Control UPLLCON 0x4C000008...
Page 34 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. SC32442B Special Registers (Sheet 5 of 14) Register Address Address Acc. Read/ Function Name (B. Endian) (L. Endian) Unit Write NAND Flash ← NFCONF 0x4E000000 NAND Flash Configuration NFCONT 0x4E000004 NAND Flash Control NFCMD 0x4E000008 NAND Flash Command...
Page 35 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-4. SC32442B Special Registers (Sheet 6 of 14) Register Address Address Acc. Read/ Function Name (B. Endian) (L. Endian) Unit Write Camera Interface ← CISRCFMT 0x4F000000 Input Source Format CIWDOFST 0x4F000004 Window offset register CIGCTRL 0x4F000008 Global control register...
Page 36 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. SC32442B Special Registers (Sheet 7 of 14) Register Address Address Acc. Read/ Function Name (B. Endian) (L. Endian) Unit Write UART ← ULCON0 0x50000000 UART 0 Line Control UCON0 0x50000004 UART 0 Control UFCON0 0x50000008 UART 0 FIFO Control...
Page 37 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-4. SC32442B Special Registers (Sheet 8 of 14) Register Address Address Acc. Read/ Function Name (B. Endian) (L. Endian) Unit Write PWM Timer ← TCFG0 0x51000000 Timer Configuration TCFG1 0x51000004 Timer Configuration TCON 0x51000008 Timer Control TCNTB0 0x5100000C...
Page 38 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. SC32442B Special Registers (Sheet 9 of 14) Register Name Address Address Acc. Read/ Function (B. Endian) (L. Endian) Unit Write USB Device FUNC_ADDR_REG 0x52000143 0x52000140 Function Address PWR_REG 0x52000147 0x52000144 Power Management EP_INT_REG 0x5200014B 0x52000148 EP Interrupt Pending and Clear...
Page 39 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-4. SC32442B Special Registers (Sheet 10 of 14) Register Name Address Address Acc. Read/Write Function (B. Endian) (L. Endian) Unit USB Device (Continued) EP2_DMA_CON 0x5200021B 0x52000218 EP2 DMA Interface Control EP2_DMA_UNIT 0x5200021F 0x5200021C EP2 DMA Tx Unit Counter EP2_DMA_FIFO 0x52000223 0x52000220...
Page 40 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. SC32442B Special Registers (Sheet 11 of 14) Register Address Address Acc. Read/ Function Name (B. Endian) Unit Write Endian) I/O port ← GPACON 0x56000000 Port A Control GPADAT 0x56000004 Port A Data GPBCON 0x56000010 Port B Control GPBDAT...
Page 41 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR Table 1-4. SC32442B Special Registers (Sheet 12 of 14) Register Address Address Acc. Read/ Function Name (B. Endian) (L. Endian) Unit Write I/O port (Continued) ← EINTFLT0 0x56000094 Reserved EINTFLT1 0x56000098 Reserved EINTFLT2 0x5600009C External Interrupt Filter Control Register 2 EINTFLT3 0x560000A0 External Interrupt Filter Control Register 3...
Page 42 SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. SC32442B Special Registers (Sheet 13 of 14) Register Address Address Acc. Unit Read/ Function Name (B. Endian) (L. Endian) Write A/D converter ← ADCCON 0x58000000 ADC Control ADCTSC 0x58000004 ADC Touch Screen Control ADCDLY 0x58000008 ADC Start or Interval Delay...
Page 43 PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR NOTES 1-42...
Page 44 SC32442B RISC MICROPROCESSOR PROGRAMMER'S MODEL PROGRAMMER'S MODEL OVERVIEW SC32442B is developed using the advanced ARM920T core, which has been designed by Advanced RISC Machines, Ltd. PROCESSOR OPERATING STATES From the programmer's point of view, the ARM920T can be in one of the two states: •...
Page 45 PROGRAMMER'S MODEL SC32442B RISC MICROPROCESSOR BIG-ENDIAN FORMAT In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24.
Page 46 SC32442B RISC MICROPROCESSOR PROGRAMMER'S MODEL OPERATING MODES ARM920T supports seven modes of operation: • User (usr): The normal ARM program execution state • FIQ (fiq): Designed to support a data transfer or channel process • IRQ (irq): Used for general-purpose interrupt handling •...
Page 47 PROGRAMMER'S MODEL SC32442B RISC MICROPROCESSOR ARM State General Registers and Program Counter System & User Supervisor Abort Undefined R10_ R11_ R12_ R13_ R13_ R13_ R13_ R13_ R14_ R14_ R14_ R14_ R14_ R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) ARM State Program Status Registers CPSR...
Page 48: Shown In Figure
SC32442B RISC MICROPROCESSOR PROGRAMMER'S MODEL The THUMB State Register Set The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR.
Page 49: Shown In Figure
PROGRAMMER'S MODEL SC32442B RISC MICROPROCESSOR The relationship between ARM and THUMB state registers The relationship between ARM and THUMB state registers are as below:- • THUMB state R0-R7 and ARM state R0-R7 are identical • THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical •...
Page 50 SC32442B RISC MICROPROCESSOR PROGRAMMER'S MODEL Accessing Hi-Registers in THUMB State In THUMB state, registers R8-R15 (“Hi registers”) are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage. A value may be transferred from a register in the range R0-R7 (a Lo register) to a Hi register and from a Hi register to a Lo register, using special variants of the MOV instruction.
Page 51 PROGRAMMER'S MODEL SC32442B RISC MICROPROCESSOR The Condition Code Flags The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed. In ARM state, all instructions may be executed conditionally: see Table 3-2 for details.
Page 52 SC32442B RISC MICROPROCESSOR PROGRAMMER'S MODEL Table 2-1. PSR Mode Bit Values M[4:0] Mode Visible THUMB state registers Visible ARM state registers 10000 User R7..R0, R14..R0, LR, SP PC, CPSR PC, CPSR 10001 R7..R0, R7..R0, LR_fiq, SP_fiq R14_fiq..R8_fiq, PC, CPSR, SPSR_fiq PC, CPSR, SPSR_fiq 10010 R7..R0,...
Page 53 PROGRAMMER'S MODEL SC32442B RISC MICROPROCESSOR EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished.
Page 54 SC32442B RISC MICROPROCESSOR PROGRAMMER'S MODEL Exception Entry/Exit Summary Table 2-2 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler. Table 2-2. Exception Entry/Exit Return Instruction Previous State Notes ARM R14_x THUMB R14_x MOV PC, R14...
Page 55 PROGRAMMER'S MODEL SC32442B RISC MICROPROCESSOR The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting I bit in the CPSR, though this can only be done from a privileged (non-User) mode.
Page 56 SC32442B RISC MICROPROCESSOR PROGRAMMER'S MODEL Software Interrupt The Software Interrupt Instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb): PC,R14_svc This restores the PC and CPSR, and returns to the instruction following the SWI.
Page 57 PROGRAMMER'S MODEL SC32442B RISC MICROPROCESSOR Exception Priorities When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1. Reset 2. Data abort 3. FIQ 4. IRQ 5. Prefetch abort Lowest priority: 6.
Page 58 SC32442B RISC MICROPROCESSOR PROGRAMMER'S MODEL INTERRUPT LATENCIES The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchronizer (Tsyncmax if asynchronous), plus the time for the longest instruction to complete (Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data abort entry (Texc), plus the time for FIQ entry (Tfiq).
Page 59 PROGRAMMER'S MODEL SC32442B RISC MICROPROCESSOR NOTES 2-16...
Page 60: Arm Instruction Set
SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET ARM INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set in the ARM920T core. FORMAT SUMMARY The following figure shows the ARM instruction set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12 11 10 9 8 7 6 5 4 3 2 1 0 Cond...
Page 61 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR NOTES Some instruction codes are not defined but does not cause Undefined instruction trap to be taken, for instance a multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their action may change in future ARM implementations.
Page 62 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET Table 3-1. The ARM Instruction Set (Continued) Mnemonic Instruction Action Move from coprocessor register to Rn: = cRn {<op>cRm} CPU register Move PSR status/flags to register Rn: = PSR Move register to PSR status/flags PSR: = Rm Rd: = Rm ×...
Page 63 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR THE CONDITION FIELD In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction's condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be executed.
Page 64 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET BRANCH AND EXCHANGE (BX) This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. This instruction performs a branch by copying the contents of a general register, Rn, into the Program Counter, PC.
Page 65 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR Examples Generate branch target address and set bit 0 high – R0, Into_THUMB + 1 hence it comes in THUMB state Branch and change to THUMB state. CODE16 Assemble subsequent code as Into_THUMB THUMB instructions Generate branch target to word aligned address ADR R5, Back_to_ARM hence bit 0 is low and so change back to ARM state.
Page 66 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET BRANCH AND BRANCH WITH LINK (B, BL) The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction encoding is shown in Figure 3-3, below. Cond Offset [24] Link bit 0 = Branch...
Page 67 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR ASSEMBLER SYNTAX Items in “{}” are optional. Items in “<>” must be present. B{L}{cond} <expression> Used to request the Branch with Link form of the instruction. If absent, R14 will not be affected by the instruction. {cond} A two-character mnemonic as shown in Table 3-2.
Page 68 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET DATA PROCESSING The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-4. 26 25 OpCode Cond Operand2 [15:12] Destination register 0 = Branch 1 = Branch with link...
Page 69 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. The first operand is always a register (Rn). The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction.
Page 70 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET CPSR FLAGS The data processing operations can be classified as logical or arithmetic. The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to produce the result.
Page 71 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR SHIFTS When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the Shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right).
Page 72 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET Contents of Rm carry out Value of Operand 2 Figure 3-7. Logical Shift Right The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output.
Page 73 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR Rotate right (ROR) operations reuse the bits which "overshoot" in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. For example, ROR #5 is shown in Figure 3-9.
Page 74 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET Register Specified Shift Amount Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any general register other than R15. If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the CPSR C flag will be passed on as the shifter carry output.
Page 75 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value. This value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field.
Page 76 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX • MOV,MVN (single operand instructions). <opcode>{cond}{S} Rd,<Op2> • CMP,CMN,TEQ,TST (instructions which do not produce a result). <opcode>{cond} Rn,<Op2> • AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC <opcode>{cond}{S} Rd,Rn,<Op2> where: <Op2> Rm{,<shift>} or,<#expression> {cond} A two-character condition mnemonic. See Table 3-2. Set condition codes if S present (implied for CMP, CMN, TEQ, TST).
Page 77 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR PSR TRANSFER (MRS, MSR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented using the TEQ, TST, CMN and CMP instructions without the S flag set.
Page 78 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET MRS (transfer PSR contents to a register) 00010 001111 Cond 000000000000 [15:12] Destination Register [22] Source PSR 0 = CPSR 1 = SPSR_<current mode> [31:28] Condition Field MSR (transfer register contents to PSR) 00010 101001111 Cond 00000000...
Page 79 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR RESERVED BITS Only twelve bits of the PSR are defined in ARM920T (N,Z,C,V,I,F, T & M[4:0]); the remaining bits are reserved for use in future versions of the processor. Refer to Figure 2-6 for a full description of the PSR bits. To ensure the maximum compatibility between ARM920T programs and future processors, the following rules should be observed: •...
Page 80 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLY SYNTAX • MRS - transfer PSR contents to a register MRS{cond} Rd,<psr> • MSR - transfer register contents to PSR MSR{cond} <psr>,Rm • MSR - transfer register contents to PSR flag bits only MSR{cond} <psrf>,Rm The most significant four bits of the register contents are written to the N,Z,C &...
Page 81 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-12. The multiply and multiply-accumulate instructions use an 8 bit Booth's algorithm to perform integer multiplication. 21 20 0 0 0 0 Cond...
Page 82 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET If the Operands Are Interpreted as Signed Operand A has the value -10, operand B has the value 20, and the result is -200 which is correctly represented as 0xFFFFFF38. If the Operands Are Interpreted as Unsigned Operand A has the value 4294967286, operand B has the value 20 and the result is 85899345720, which is represented as 0x13FFFFFF38, so the least significant 32 bits are 0xFFFFFF38.
Page 83 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z (Zero) flags are set correctly on the result (N is made equal to bit 31 of the result, and Z is set if and only if the result is zero).
Page 84 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL, MLAL) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-13. The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results. Signed and unsigned multiplication each with optional accumulate give rise to four variations.
Page 85 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR OPERAND RESTRICTIONS • R15 must not be used as an operand or as a destination register. • RdHi, RdLo, and Rm must all specify different registers. CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N and Z flags are set correctly on the result (N is equal to bit 63 of the result, Z is set if and only if all 64 bits of the result are zero).
Page 86 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX Table 3-5. Assembler Syntax Descriptions Mnemonic Description Purpose UMULL{cond}{S} RdLo,RdHi,Rm,Rs Unsigned Multiply Long 32 x 32 = 64 UMLAL{cond}{S} RdLo,RdHi,Rm,Rs Unsigned Multiply & Accumulate Long 32 x 32 + 64 = 64 SMULL{cond}{S} RdLo,RdHi,Rm,Rs Signed Multiply Long 32 x 32 = 64...
Page 87 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR SINGLE DATA TRANSFER (LDR, STR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-14. The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register.
Page 88 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET OFFSETS AND AUTO-INDEXING The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). The offset may be added to (U=1) or subtracted from (U=0) the base register Rn.
Page 89 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR memory register LDR from word aligned address memory register LDR from address offset by 2 Figure 3-15. Little-Endian Offset Addressing Big-Endian Configuration A byte load (LDRB) expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary, on data bus inputs 23 through 16 if it is a word address plus one byte, and so on.
Page 90 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET USE OF R15 Write-back must not be specified if R15 is specified as the base register (Rn). While using R15 as the base register, you must remember it contains an address of 8 bytes on from the address of the current instruction. R15 must not be specified as the register offset (Rm).
Page 91 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR ASSEMBLER SYNTAX <LDR|STR>{cond}{B}{T} Rd,<Address> where: Load from memory into a register Store from a register into memory {cond} Two-character condition mnemonic. See Table 3-2. If B is present then byte transfer, otherwise word transfer If T is present the W bit will be set in a post-indexed instruction, forcing non-privileged mode for the transfer cycle.
Page 92 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET EXAMPLES R1,[R2,R4]! ; Store R1 at R2+R4 (both of which are registers) ; and write back address to R2. R1,[R2],R4 ; Store R1 at R2 and write back R2+R4 to R2. R1,[R2,#16] ; Load R1 from contents of R2+16, but don't write back. R1,[R2,R3,LSL#2] ;...
Page 93: Store To Memory
ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR HALFWORD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-16. These instructions are used to load or store half-words of data and also load sign-extended bytes or half-words of data.
Page 94 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET 8 7 6 5 4 3 Offset S H 1 Offset Cond [3:0] Immediate Offset (Low Nibble) [6][5] S H 0 0 = SWP instruction 0 1 = Unsigned halfword 1 1 = Signed byte 1 1 = Signed halfword [11:8] Immediate Offset (High Nibble) [15:12] Source/Destination Register...
Page 95 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR HALFWORD LOAD AND STORES Setting S=0 and H=1 may be used to transfer unsigned Half-words between an ARM920T register and memory. The action of LDRH and STRH instructions is influenced by the BIGEND control signal. The two possible configurations are described in the section below.
Page 96 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET Big-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte.
Page 97 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR ASSEMBLER SYNTAX <LDR|STR>{cond}<H|SH|SB> Rd,<address> Load from memory into a register Store from a register into memory {cond} Two-character condition mnemonic. See Table 3-2.. Transfer halfword quantity Load sign extended byte (Only valid for LDR) Load sign extended halfword (Only valid for LDR) An expression evaluating to a valid register number.
Page 98 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET EXAMPLES LDRH R1,[R2,-R3]! ; Load R1 from the contents of the halfword address ; contained in R2-R3 (both of which are registers) ; and write back address to R2 STRH R3,[R4,#14] ; Store the halfword in R3 at R14+14 but don't write back. LDRSB R8,[R2],#-223 ;...
Page 99 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR BLOCK DATA TRANSFER (LDM, STM) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-18. Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible registers. They support all possible stacking modes, maintaining full or empty stacks which can grow up or down memory, and are very efficient instructions for saving or restoring context, or for moving large blocks of data around main memory.
Page 100 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET ADDRESSING MODES The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the up/ down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last.
Page 101 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 Figure 3-20. Pre-Increment Addressing 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 Figure 3-21. Post-Decrement Addressing 3-42...
Page 102 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 Figure 3-22. Pre-Decrement Addressing USE OF THE S BIT When the S bit is set in a LDM/STM instruction it depends on R15 is available in the transfer list and on the type of instruction.
Page 103 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR INCLUSION OF THE BASE IN THE REGISTER LIST When write-back is specified, the base is written back at the end of the second cycle of the instruction. During a STM, the first register is written out at the start of the second cycle. A STM which includes storing the base, with the base as the first register to be stored, will therefore store the unchanged value, whereas with the base second or later in the transfer order, will store the modified value.
Page 104 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX <LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{^} where: {cond} Two character condition mnemonic. See Table 3-2. An expression evaluating to a valid register number <Rlist> A list of registers and register ranges enclosed in {} (e.g. {R0,R2-R7,R10}). If present requests write-back (W=1), otherwise W=0.
Page 105 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR EXAMPLES LDMFD SP!,{R0,R1,R2} ; Unstack 3 registers. STMIA R0,{R0-R15} ; Save all registers. ; R15 ← (SP), CPSR unchanged. LDMFD SP!,{R15} ; R15 ← (SP), CPSR <- SPSR_mode LDMFD SP!,{R15}^ ; (allowed only in privileged modes). STMFD R13,{R0-R14}^ ;...
Page 106 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET SINGLE DATA SWAP (SWP) Cond 00010 0000 1001 [3:0] Source Register [15:12] Destination Register [19:16] Base Register [22] Byte/Word Bit 0 = Swap word quantity 1 = Swap word quantity [31:28] Condition Field Figure 3-23. Swap Instruction The instruction is only executed if the condition is true.
Page 107 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR USE OF R15 Do not use R15 as an operand (Rd, Rn or Rs) in a SWP instruction. DATA ABORTS If the address used for the swap is unacceptable to a memory management system, the memory manager can flag the problem by driving ABORT HIGH.
Page 108 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET SOFTWARE INTERRUPT (SWI) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-24, below. Cond 1111 Comment Field (Ignored by Processor) [31:28] Condition Field Figure 3-24.
Page 109 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR ASSEMBLER SYNTAX SWI{cond} <expression> {cond} Two character condition mnemonic, Table 3-2. <expression> Evaluated and placed in the comment field (which is ignored by ARM920T). Examples ReadC ; Get next character from read stream. WriteI+"k” ;...
Page 110 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET COPROCESSOR DATA OPERATIONS (CDP) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-25. This class of instruction is used to tell a coprocessor to perform some internal operation. No result is communicated back to ARM920T, and it will not wait for the operation to complete.
Page 111 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S + bI incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. S and I are defined as sequential (S-cycle) and internal (I-cycle). Assembler syntax CDP{cond} p#,<expression1>,cd,cn,cm{,<expression2>} {cond}...
Page 112 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET COPROCESSOR DATA TRANSFERS (LDC, STC) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-26. This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessors's registers directly to memory.
Page 113 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR THE COPROCESSOR FIELDS The CP# field is used to identify the coprocessor which is required to supply or accept the data, and a coprocessor will only respond if its number matches the contents of this field. The CRd field and the N bit contain information for the coprocessor which may be interpreted in different ways by different coprocessors, but by convention CRd is the register to be transferred (or the first register where more than one is to be transferred), and the N bit is used to choose one of two transfer length options.
Page 114 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX <LDC|STC>{cond}{L} p#,cd,<Address> Load from memory to coprocessor Store from coprocessor to memory When present perform long transfer (N=1), otherwise perform short transfer (N=0) {cond} Two character condition mnemonic. See Table 3-2.. The unique number of the required coprocessor An expression evaluating to a valid coprocessor register number that is placed in the CRd field <Address>...
Page 115 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR COPROCESSOR REGISTER TRANSFERS (MRC, MCR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-27. This class of instruction is used to communicate information directly between ARM920T and a coprocessor. An example of a coprocessor to ARM920T register transfer (MRC) instruction would be a FIX of a floating point value held in a coprocessor, where the floating point number is converted into a 32 bit integer within the coprocessor, and the result is then transferred to ARM920T register.
Page 116 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET TRANSFERS TO R15 When a coprocessor register transfer to ARM920T has R15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the N, Z, C and V flags respectively. The other bits of the transferred word are ignored, and the PC and other CPSR bits are unaffected by the transfer.
Page 117 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR UNDEFINED INSTRUCTION The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction format is shown in Figure 3-28. 25 24 5 4 3 xxxxxxxxxxxxxxxxxxxx xxxx Cond Figure 3-28.
Page 118 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION SET EXAMPLES The following examples show ways in which the basic ARM920T instructions can combine to give efficient code. None of these methods saves a great deal of execution time (although they may save some), mostly they just save code.
Page 119 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR Division and Remainder A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross Development Toolkit, available from your supplier. A short general purpose divide routine follows.
Page 120 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET 5. Overflow in unsigned multiply accumulate with a 64 bit result UMULL Rl,Rh,Rm,Rn ; 3 to 6 cycles ADDS Rl,Rl,Ra1 ; Lower accumulate Rh,Rh,Ra2 ; Upper accumulate overflow ; 1 cycle and 2 registers 6.
Page 121 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR Multiplication by 6 Ra,Ra,Ra,LSL #1 ; Multiply by 3 Ra,Ra,LSL#1 ; and then by 2 Multiply by 10 and add in extra number Ra,Ra,Ra,LSL#2 ; Multiply by 5 Ra,Rc,Ra,LSL#1 ; Multiply by 2 and add in next digit General recursive method for Rb := Ra*C, C a constant: 1.
Page 122 SC32442B RISC MICROPROCESSOR ARM INSTRUCTION SET LOADING A WORD FROM AN UNKNOWN ALIGNMENT ; Enter with address in Ra (32 bits) uses ; Rb, Rc result in Rd. Note d must be less than c e.g. 0,1 Rb,Ra,#3 ; Get word aligned address LDMIA Rb,{Rd,Rc} ;...
Page 123 ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR NOTES 3-64...
Page 124: Thumb Instruction Set
SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET THUMB INSTRUCTION SET THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16-bit versions of ARM instruction sets (32-bit format). The ARM instructions are reduced to 16-bit versions.Thumb instructions, at the cost of versatile functions of the ARM instruction sets. The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM920T core.
Page 125 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure. 15 14 13 12 11 10 Offset5 Move Shifted register Rn/offset3 Add/subtract Offset8 Move/compare/add/ subtract immediate ALU operations H1 H2 Rs/Hs Rd/Hd Hi register operations /branch exchange...
Page 126 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET OPCODE SUMMARY The following table summarizes the THUMB instruction set. For further information about a particular instruction please refer to the sections listed in the right-most column. Table 4-1. THUMB Instruction Set Opcodes Mnemonic Instruction Lo-Register Hi-Register...
Page 127 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR Table 4-1. THUMB Instruction Set Opcodes (Continued) Mnemonic Instruction Lo-Register Hi-Register Condition Operand Operand Codes Set Negate – – Pop register – – PUSH Push register – – Rotate Right – Subtract with Carry –...
Page 128 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 1: MOVE SHIFTED REGISTER Offset5 [2:0] Destination Register [5:3] Source Register [10:6] Immediate Vale [12:11] Opcode 0 = LSL 1 = LSR 2 = ASR Figure 4-2. Format 1 OPERATION These instructions move a shifted value between Lo registers. The THUMB assembler syntax is shown in Table 4-2.
Page 129 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-2. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LSR R2, R5, #27 ;...
Page 130 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 2: ADD/SUBTRACT Rn/Offset3 [2:0] Destination Register [5:3] Source Register [8:6] Register/Immediate Vale [9] Opcode 0 = ADD 1 = SUB [10] Immediate Flag 0 = Register operand 1 = Immediate oerand Figure 4-3. Format 2 OPERATION These instructions allow the contents of a Lo register or a 3-bit immediate value to be added to or subtracted from a Lo register.
Page 131 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-3. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES R0, R3, R4 ;...
Page 132 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE Offset8 [7:0] Immediate Vale [10:8] Source/Destination Register [12:11] Opcode 0 = MOV 1 = CMP 2 = ADD 3 = SUB Figure 4-4. Format 3 OPERATIONS The instructions in this group perform operations between a Lo register and an 8-bit immediate value. The THUMB assembler syntax is shown in Table 4-4.
Page 133 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-4. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES R0, #128 ;...
Page 134 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 4: ALU OPERATIONS [2:0] Source/Destination Register [5:3] Source Register 2 [9:6] Opcode Figure 4-5. Format 4 OPERATION The following instructions perform ALU operations on a Lo register pair. NOTE All instructions in this group set the CPSR condition codes. Table 4-5.
Page 135 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-5. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES R3, R4 ;...
Page 136 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE Rs/Hs Rd/Hd [2:0] Destination Register [5:3] Source Register [6] Hi Operand Flag 2 [7] Hi Operand Flag 1 [9:8] Opcode Figure 4-6. Format 5 OPERATION There are four sets of instructions in this group. The first three allow ADD, CMP and MOV operations to be performed between Lo and Hi registers, or a pair of Hi registers.
Page 137 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR Table 4-6. Summary of Format 5 Instructions (Continued) THUMB assembler ARM equivalent Description CMP Hd, Hs CMP Hd, Hs Compare two registers in the range 8-15. Set the condition code flags on the result. MOV Rd, Hs MOV Rd, Hs Move a value from a register in the...
Page 138 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET EXAMPLES Hi-Register Operations PC, R5 ; PC := PC + R5 but don't set the condition codes. R4, R12 ; Set the condition codes on the result of R4 - R12. R15, R14 ; Move R14 (LR) into R15 (PC) but don't set the condition codes, eg.
Page 139 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR FORMAT 6: PC-RELATIVE LOAD Word 8 [7:0] Immediate Value [10:8] Destination Register Figure 4-7. Format 6 OPERATION This instruction loads a word from an address specified as a 10-bit immediate offset from the PC. The THUMB assembler syntax is shown below.
Page 140 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LDR R3,[PC,#844] ; Load into R3 the word found at the address formed by adding 844 to PC.bit[1] of PC is forced to zero.
Page 141: Transfer Word Quantity
THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR FORMAT 7: LOAD/STORE WITH REGISTER OFFSET [2:0] Source/Destination Register [5:3] Base Register [8:6] Offset Register [10] Byte/Word Flag 0 = Transfer word quantity 1 = Transfer byte quantity [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 4-8.
Page 142 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET OPERATION These instructions transfer byte or word values between registers and memory. Memory addresses are pre- indexed using an offset register in the range 0-7. The THUMB assembler syntax is shown in Table 4-8. Table 4-8.
Page 143 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR FORMAT 8: LOAD/STORE SIGN-EXTENDED BYTE/HALFWORD [2:0] Destination Register [5:3] Base Register [8:6] Offset Register [10] Sign-Extended Flag 0 = Operand not sing-extended 1 = Operand sing-extended [11] H Flag Figure 4-9. Format 8 OPERATION These instructions load optionally sign-extended bytes or halfwords, and store halfwords.
Page 144 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-9. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STRH R4, [R3, R0]...
Page 145 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR FORMAT 9: LOAD/STORE WITH IMMEDIATE OFFSET Offset5 [2:0] Source/Destination Register [5:3] Base Register [10:6] Offset Register [11] Load/Store Flag 0 = Store to memory 1 = Load from memory [12] Byte/Word Flad 0 = Transfer word quantity 1 = Transfer byte quantity Figure 4-10.
Page 146 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7-bit offset. The THUMB assembler syntax is shown in Table 4-10. Table 4-10. Summary of Format 9 Instructions THUMB assembler ARM equivalent Description...
Page 147 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR FORMAT 10: LOAD/STORE HALFWORD Offset5 [2:0] Source/Destination Register [5:3] Base Register [10:6] Immediate Value [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 4-11. Format 10 OPERATION These instructions transfer halfword values between a Lo register and memory. Addresses are pre-indexed, using a 6-bit immediate value.
Page 148 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-11. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STRH R6, [R1, #56]...
Page 149 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR FORMAT 11: SP-RELATIVE LOAD/STORE Word 8 [7:0] Immediate Value [10:8] Destination Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 4-12. Format 11 OPERATION The instructions in this group perform an SP-relative load or store. The THUMB assembler syntax is shown in the following table.
Page 150 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-12. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES R4, [SP,#492] ;...
Page 151 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR FORMAT 12: LOAD ADDRESS Word 8 [7:0] 8-bit Unsigned Constant [10:8] Destination Register [11] Source 0 = PC 1 = SP Figure 4-13. Format 12 OPERATION These instructions calculate an address by adding a 10-bit constant to either the PC or the SP, and load the resulting address into a register.
Page 152 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-13. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES R2, PC, #572 ;...
Page 153 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR FORMAT 13: ADD OFFSET TO STACK POINTER SWord 7 [6:0] 7-bit Immediate Value [7] Sign Flag 0 = Offset is positive 1 = Offset is negative Figure 4-14. Format 13 OPERATION This instruction adds a 9-bit signed constant to the stack pointer. The following table shows the THUMB assembler syntax.
Page 154 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 14: PUSH/POP REGISTERS Rlist [7:0] Register List [8] PC/LR Bit 0 = Do not store LR/Load PC 1 = Store LR/Load PC [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 4-15.
Page 155 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-15. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES PUSH {R0-R4,LR}...
Page 156 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 15: MULTIPLE LOAD/STORE Rlist [7:0] Register List [10:8] Base Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 4-16. Format 15 OPERATION These instructions allow multiple loading and storing of Lo registers. The THUMB assembler syntax is shown in the following table.
Page 157 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR FORMAT 16: CONDITIONAL BRANCH SOffset 8 Cond [7:0] 8-bit Signed Immediate [11:8] Condition Figure 4-17. Format 16 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes.
Page 158 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET Table 4-17. The Conditional Branch Instructions (Continued) THUMB assembler ARM equivalent Description 1001 BLS label BLS label Branch if C clear or Z set (unsigned lower or same) 1010 BGE label BGE label Branch if N set and V set, or N clear and V clear (greater or equal) 1011 BLT label...
Page 159 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR FORMAT 17: SOFTWARE INTERRUPT Value 8 [7:0] Comment Field Figure 4-18. Format 17 OPERATION The SWI instruction performs a software interrupt. On taking the SWI, the processor switches into ARM state and enters Supervisor (SVC) mode. The THUMB assembler syntax for this instruction is shown below.
Page 160 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 18: UNCONDITIONAL BRANCH Offset11 [10:0] Immediate Value Figure 4-19. Format 18 OPERATION This instruction performs a PC-relative Branch. The THUMB assembler syntax is shown below. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction.
Page 161 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR FORMAT 19: LONG BRANCH WITH LINK Offset [10:0] Long Branch and Link Offset High/Low [11] Low/High Offset Bit 0 = Offset high 1 = Offset low Figure 4-20. Format 19 OPERATION This format specifies a long branch with link. The assembler splits the 23-bit two's complement half-word offset specified by the label into two 11-bit halves, ignoring bit 0 (which must be 0), and creates two THUMB instructions.
Page 162 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction. Table 4-20. The BL Instruction THUMB assembler ARM equivalent Description BL label none LR := PC + OffsetHigh << 12 temp := next instruction address PC := LR + OffsetLow <<...
Page 163 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code. Each example also shows the ARM equivalent so these may be compared. MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following instructions are the code to multiply by various constants using 1, 2 or 3 Thumb instructions alongside the ARM equivalents.
Page 164 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code. Thumb code ;signed_divide ; Signed divide of R1 by R0: returns quotient in R0, ;...
Page 165 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR Now fix up the signs of the quotient (R0) and remainder (R1) {R2, R3} ; Get dividend/divisor signs back R3, R2 ; Result sign R0, R3 ; Negate if result sign = - 1 R0, R3 R1, R2 ;...
Page 166 SC32442B RISC MICROPROCESSOR THUMB INSTRUCTION SET DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code.
Page 167 THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR NOTES 4-44...
Page 168: Memory Controller
SC32442B RISC MICROPROCESSOR MEMORY CONTROLLER MEMORY CONTROLLER OVERVIEW The SC32442B memory controller provides memory control signals that are required for external memory access. The SC32442B has the following features: — Little/Big endian (selectable by a software) — Address space: 128Mbytes per bank (total 1GB/8 banks) —...
Page 169 MEMORY CONTROLLER SC32442B RISC MICROPROCESSOR OM[1:0] = 00 OM[1:0] = 01,10 0x40000_0000 SROM/SDRAM SROM/SDRAM 2MB/4MB/8MB/16MB (nGCS7) (nGCS7) /32MB/64MB/128MB Refer to 0x3800_0000 Table 5-1 2MB/4MB/8MB/16MB SROM/SDRAM SROM/SDRAM /32MB/64MB/128MB (nGCS6) (nGCS6) 0x3000_0000 SROM SROM 128MB (nGCS5) (nGCS5) 0x2800_0000 SROM SROM 128MB (nGCS4) (nGCS4) HADDR[29:0] 0x2000_0000...
Page 170: Function Description
SC32442B RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 FUNCTION DESCRIPTION BANK0 BUS WIDTH The data bus of BANK0 (nGCS0) should be configured with a width as one of 16-bit and 32-bit ones. Because the BANK0 works as the booting ROM bank (map to 0x0000_0000), the bus width of BANK0 should be determined before the first ROM access, which will depend on the logic level of OM[1:0] at Reset.
Page 171 MEMORY CONTROLLER SC32442B RISC MICROPROCESSOR SDRAM BANK ADDRESS PIN CONNECTION EXAMPLE Table 5-2. SDRAM Bank Address Configuration Example Bank Size Bus Width Base Component Memory Configuration Bank Address 2MByte 16Mbit (1M x 8 x 2Bank) x 1 (512K x 16 x 2B) x 1 (1M x 8 x 2B) x 2 (1M x 8 x 2B) x 2 16Mb...
Page 172 SC32442B RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 nWAIT PIN OPERATION If the WAIT bit(WSn bit in BWSCON) corresponding to each memory bank is enabled, the nOE duration should be prolonged by the external nWAIT pin while the memory bank is active. nWAIT is checked from tacc-1. nOE will be de-asserted at the next clock after sampling nWAIT is high.
Page 173 MEMORY CONTROLLER SC32442B RISC MICROPROCESSOR nXBREQ/nXBACK Pin Operation If nXBREQ is asserted, the SC32442B will respond by lowering nXBACK. If nXBACK=L, the address/data bus and memory control signals are in Hi-Z state as shown in Table 1-1. After nXBREQ is de-asserted, the nXBACK will also be de-asserted.
Page 174 SC32442B RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 ROM Memory Interface Examples nGCSn Figure 5-4. Memory Interface with 8-bit ROM nWBE1 nWBE0 nGCSn nGCSn Figure 5-5. Memory Interface with 8-bit ROM x 2...
Page 175 MEMORY CONTROLLER SC32442B RISC MICROPROCESSOR nWBE0 nWBE1 nWBE2 nWBE3 nGCSn nGCSn nGCSn nGCSn Figure 5-6. Memory Interface with 8-bit ROM x 4 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nGCSn Figure 5-7. Memory Interface with 16-bit ROM...
Page 176 SC32442B RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 SRAM Memory Interface Examples DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nGCSn nBE1 nBE0 Figure 5-8. Memory Interface with 16-bit SRAM DQ10 DQ10 DQ11 DQ11 DQ12 DQ12 DQ13 DQ13 DQ14 DQ14 DQ15 DQ15 nGCSn nGCSn nBE1 nBE3...
Page 177 MEMORY CONTROLLER SC32442B RISC MICROPROCESSOR SDRAM Memory Interface Examples DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM0 LDQM DQM1 UDQM nSCS nSCS0 SCKE SCKE nSRAS nSRAS SCLK SCLK nSCAS nSCAS Figure 5-10. Memory Interface with 16-bit SDRAM (4Mx16, 4banks) DQ10 DQ10 DQ11 DQ11 DQ12...
Page 178 SC32442B RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 PROGRAMMABLE ACCESS CYCLE HCLK A[24:0] nGCS Tacs Tcah Tcos Tacc Tacp Tcoh nWBE D[31:0](R) D[31:0] (W) Tacs = 1 cycle Tacp = 2 cycles Tcos = 1 cycle Tcoh = 1 cycle Tacc = 3 cycles Tcah = 2 cycles Figure 5-12.
Page 179 MEMORY CONTROLLER SC32442B RISC MICROPROCESSOR MCLK SCKE nSCS nSRAS nSCAS Trcd ADDR A10/AP DATA (CL2) DATA (CL3) Bank Write Read (CL = 2, CL = 3, BL = 1) Precharge Active Trp = 2 cycle Tcas = 2 cycle Trcd = 2 cycle Tcp = 2 cycle Figure 5-13.
Page 180 SC32442B RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) Register Address Description Reset Value BWSCON 0x48000000 Bus width & wait status control register 0x000000 BWSCON Description Initial state [31] Determines SRAM for using UB/LB for bank 7. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) [30]...
Page 181 MEMORY CONTROLLER SC32442B RISC MICROPROCESSOR BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) (Continued) [10] Determines WAIT status for bank 2. 0 = WAIT disable 1 = WAIT enable [9:8] Determines data bus width for bank 2. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved Determines SRAM for using UB/LB for bank 1.
Page 182 SC32442B RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 BANK CONTROL REGISTER (BANKCONn: nGCS0-nGCS5) Register Address Description Reset Value BANKCON0 0x48000004 Bank 0 control register 0x0700 BANKCON1 0x48000008 Bank 1 control register 0x0700 BANKCON2 0x4800000C Bank 2 control register 0x0700 BANKCON3 0x48000010 Bank 3 control register 0x0700 BANKCON4...
Page 183 MEMORY CONTROLLER SC32442B RISC MICROPROCESSOR BANK CONTROL REGISTER (BANKCONn: nGCS6-nGCS7) Register Address Description Reset Value BANKCON6 0x4800001C Bank 6 control register 0x18008 BANKCON7 0x48000020 Bank 7 control register 0x18008 BANKCONn Description Initial State [16:15] Determine the memory type for bank6 and bank7. 00 = ROM or SRAM 01 = Reserved (Do not use) 10 = Reserved (Do not use)
Page 184 SC32442B RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 REFRESH CONTROL REGISTER Register Address Description Reset Value REFRESH 0x48000024 SDRAM refresh control register 0xac0000 REFRESH Description Initial State REFEN [23] SDRAM Refresh Enable 0 = Disable 1 = Enable (self or CBR/auto refresh) TREFMD [22] SDRAM Refresh Mode...
Page 185 MEMORY CONTROLLER SC32442B RISC MICROPROCESSOR BANKSIZE REGISTER Register Address Description Reset Value BANKSIZE 0x48000028 Flexible bank size register BANKSIZE Description Initial State BURST_EN ARM core burst operation enable. 0 = Disable burst operation. 1 = Enable burst operation. Reserved Not used SDRAM power down mode enable control by SCKE SCKE_EN 0 = SDRAM power down mode disable...
Page 186 SC32442B RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 SDRAM MODE REGISTER SET REGISTER (MRSR) Register Address Description Reset Value MRSRB6 0x4800002C Mode register set register bank6 MRSRB7 0x48000030 Mode register set register bank7 MRSR Description Initial State Reserved [11:10] Not used Write burst length 0: Burst (Fixed) 1: Reserved...
Page 187 MEMORY CONTROLLER SC32442B RISC MICROPROCESSOR NOTES 5-20...
Page 188 SC32442B RISC MICROPROCESSOR NAND FLASH CONTROLLER NAND FLASH CONTORLLER OVERVIEW In recent times, NOR flash memory gets high in price while an SDRAM and a NAND flash memory is comparatively economical , motivating some users to execute the boot code on a NAND flash and execute the main code on an SDRAM.
Page 189 NAND FLASH CONTROLLER SC32442B RISC MICROPROCESSOR BLOCK DIAGRAM nFCE ECC Gen. NAND FLASH nFRE Interface nFWE Control & FRnB State Machine I/O0 - I/O15 Slave I/F Stepping Stone Stepping Stone Controller (4KB SRAM) Figure 6-1 NAND Flash Controller Block Diagram BOOT LOADER FUNCTION AUTO BOOT REGISTERS...
Page 190 SC32442B RISC MICROPROCESSOR NAND FLASH CONTROLLER PIN CONFIGURATION OM[1:0] = 00: Enable NAND flash memory boot NCON : NAND flash memory selection(Normal / Advance) 0: Normal NAND flash(256Words/512Bytes page size, 3/4 address cycle) 1: Advance NAND flash(1KWords/2KBytes page size, 4/5 address cycle) GPG13 : NAND flash memory page capacitance selection 0: Page=256Words(NCON = 0) or Page=1KWords(NCON = 1) 1: Page=512Bytes(NCON = 0) or Page=2KBytes(NCON = 1)
Page 191 NAND FLASH CONTROLLER SC32442B RISC MICROPROCESSOR NAND FLASH MEMORY TIMING TACLS TWRPH0 TWRPH1 HCLK CLE / ALE DATA COMMAND / ADDRESS Figure 6-3. CLE & ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0) TWRPH0 TWRPH1 HCLK nWE / nRE DATA DATA Figure 6-4 nWE & nRE Timing (TWRPH0=0, TWRPH1=0)
Page 192 SC32442B RISC MICROPROCESSOR NAND FLASH CONTROLLER SOFTWARE MODE SC32442B supports only software mode access. Using this mode, you can completely access the NAND flash memory. The NAND Flash Controller supports direct access interface with the NAND flash memory. 1) Writing to the command register = the NAND Flash Memory command cycle 2) Writing to the address register = the NAND Flash Memory address cycle 3) Writing to the data register = write data to the NAND Flash Memory (write cycle) 4) Reading from the data register = read data from the NAND Flash Memory (read cycle)
Page 193 NAND FLASH CONTROLLER SC32442B RISC MICROPROCESSOR Data Register Configuration 1) 16-bit NAND Flash Memory Interface A. Word Access Register Endian Bit [31:24] Bit [23:16] Bit [15:8] Bit [7:0] NFDATA Little I/O[15:8] I/O[ 7:0] I/O[15:8] I/O[ 7:0] NFDATA I/O[15:8] I/O[ 7:0] I/O[15:8] I/O[ 7:0] B.
Page 194 SC32442B RISC MICROPROCESSOR NAND FLASH CONTROLLER ECC(Error Correction Code) NAND Flash controller consists of four ECC (Error Correction Code) modules. The two ECC modules (one for data[7:0] and the other for data[15:8]) can be used for (up to) 2048 bytes ECC Parity code generation, and the others(one for data[7:0] and the other for data[15:8]) can be used for (up to) 16 bytes ECC Parity code generation.
Page 195 NAND FLASH CONTROLLER SC32442B RISC MICROPROCESSOR ECC MODULE FEATURES ECC generation is controlled by the ECC Lock (MainECCLock, SpareECCLock) bit of the Control register. ECC Register Configuration (Little / Big Endian) 1) 16-bit NAND Flash Memory Interface Register Bit [31:24] Bit [23:16] Bit [15:8] Bit [7:0]...
Page 196 SC32442B RISC MICROPROCESSOR NAND FLASH CONTROLLER to Spare area, which value will be the same as NFMECC0/1) and which is generated from the main data area. NAND FLASH MEMORY MAPPING 0xFFFF_FFFF Not Used Not Used 0x6000_0000 SFR Area SFR Area 0x4800_0000 0x4000_0FFF Not Used...
Page 197 NAND FLASH CONTROLLER SC32442B RISC MICROPROCESSOR NAND FLASH MEMORY CONFIGURATION R/ B I/O7 DATA[7] nFRE I/O6 DATA[6] nFCE I/O5 DATA[5] I/O4 DATA[4] I/O3 DATA[3] nFWE I/O2 DATA[2] I/O1 DATA[1] I/O0 DATA[0] Figure 6-1 A 8-bit NAND Flash Memory Interface When you write the address, the same address is issued from data[7:0] and data[15:8] Rn B R/ B I/O7...
Page 198 SC32442B RISC MICROPROCESSOR NAND FLASH CONTROLLER Nand Flash configuration Register Register Address Description Reset Value NFCONF 0x4E000000 NAND Flash Configuration register 0x0000100X NFCONF Description Initial State Reserved [15:14] Reserved TACLS [13:12] CLE & ALE duration setting value (0~3) Duration = HCLK x TACLS Reserved [11] Reserved...
Page 199 NAND FLASH CONTROLLER SC32442B RISC MICROPROCESSOR AdvFlash (Read only) Advance NAND flash memory for auto-booting H/W Set 0: Support 256 or 512 byte/page NAND flash memory (NCON0) 1: Support 1024 or 2048 byte/page NAND flash memory This bit is determined by NCON0 pin status during reset and wake-up from sleep mode.
Page 200 SC32442B RISC MICROPROCESSOR NAND FLASH CONTROLLER CONTROL REGISTER Register Address Description Reset Value NFCONT 0x4E000004 NAND Flash control register 0x0384 NFCONT Description Initial State Reserved [14:15] Reserved Lock-tight [13] Lock-tight configuration 0: Disable lock-tight 1: Enable lock-tight, Once this bit is set to 1, you cannot clear. Only reset or wake up from sleep mode can make this bit disable(can not cleared by software).
Page 201 NAND FLASH CONTROLLER SC32442B RISC MICROPROCESSOR 0: Unlock Spare ECC 1: Lock Spare ECC Spare area ECC status register is NFSECC(0x4E000034), MainECCLock Lock Main data area ECC generation 0: Unlock Main data area ECC generation 1: Lock Main data area ECC generation Main area ECC status register is NFMECC0/1(0x4E00002C/30), InitECC...
Page 202 SC32442B RISC MICROPROCESSOR NAND FLASH CONTROLLER COMMAND REGISTER Register Address Description Reset Value NFCMMD 0x4E000008 NAND Flash command set register 0x00 NFCMMD Description Initial State Reserved [15:8] Reserved 0x00 NFCMMD [7:0] NAND Flash memory command value 0x00 ADDRESS REGISTER Register Address Description Reset Value...
Page 203 NAND FLASH CONTROLLER SC32442B RISC MICROPROCESSOR MAIN DATA AREA REGISTER Register Address Description Reset Value NFMECCD0 0x4E000014 NAND Flash ECC 1 and 2 register for main data read 0x00000000 Note: Refer to ECC MODULE FEATURES in Page 6-8. NFMECCD1 0x4E000018 NAND Flash ECC 3 register for main data read 0x00000000...
Page 204 SC32442B RISC MICROPROCESSOR NAND FLASH CONTROLLER SPARE AREA ECC REGISTER Register Address Description Reset Value NFSECCD 0x4E00001C R/W NAND Flash ECC(Error Correction Code) register for spare 0x00000000 area data read NFSECCD Description Initial State ECCData1_1 [31:24] ECC for I/O[15:8] 0x00 ECCData1_0 [23:16] ECC for I/O[ 7:0]...
Page 205 NAND FLASH CONTROLLER SC32442B RISC MICROPROCESSOR NFCON STATUS REGISTER Register Address Description Reset Value NFSTAT 0x4E000020 R/W NAND Flash operation status register 0xXX00 NFSTAT Description Initial State Reserved Reserved Reserved [4:6] Reserved IllegalAccess Once Soft Lock or Lock-tight is enabled, The illegal access (program, erase) to the memory makes this bit set.
Page 206 SC32442B RISC MICROPROCESSOR NAND FLASH CONTROLLER ECC0/1 STATUS REGISTER Register Address Description Reset Value NFESTAT0 0x4E000024 R/W NAND Flash ECC Status register for I/O [7:0] 0x00000000 NFESTAT1 0x4E000028 R/W NAND Flash ECC Status register for I/O [15:8] 0x00000000 NFESTAT0 Description Initial State SErrorDataNo [24:21]...
Page 207 NAND FLASH CONTROLLER SC32442B RISC MICROPROCESSOR MAIN DATA AREA ECC0 STATUS REGISTER Register Address Description Reset Value NFMECC0 0x4E00002C NAND Flash ECC register for data[7:0] 0xXXXXXX NFMECC1 0x4E000030 NAND Flash ECC register for data[15:8] 0xXXXXXX NFMECC0 Description Initial State MECC0_3 [31:24] ECC3 for data[7:0] 0xXX...
Page 208 SC32442B RISC MICROPROCESSOR NAND FLASH CONTROLLER BLOCK ADDRESS REGISTER Register Address Description Reset Value NFSBLK 0x4E000038 NAND Flash programmable start block address 0x000000 NFEBLK 0x4E00003C NAND Flash programmable end block address 0x000000 Nand Flash can be programmed between start and end address.
Page 209 NAND FLASH CONTROLLER SC32442B RISC MICROPROCESSOR The NFSLK and NFEBLK can be changed while Soft lock bit(NFCONT[12]) is enabled. But cannot be changed when Lock-tight bit(NFCONT[13]) is set. NAND flash memory When NFSBLK=NFEBLK Address Locked area High (Read only) NFEBLK NFEBLK-1 Prorammable/ NFSBLK...
Page 210 SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT CLOCK & POWER MANAGEMENT OVERVIEW The Clock & Power management block consists of three parts: Clock control, USB control, and Power control. The Clock control logic in SC32442B can generate the required clock signals including FCLK for CPU, HCLK for the AHB bus peripherals, and PCLK for the APB bus peripherals.
Page 211: Functional Description
CLOCK & POWER MANAGEMENT SC32442B RISC MICROPROCESSOR FUNCTIONAL DESCRIPTION CLOCK ARCHITECTURE Figure 7-1 shows a block diagram of the clock architecture. The main clock source comes from an external crystal (XTIpll) or an external clock (EXTCLK). The clock generator includes an oscillator (Oscillation Amplifier), which is connected to an external crystal, and also has two PLLs (Phase-Locked-Loop), which generate the high frequency clock required in the SC32442B.
Page 212 SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT P[5:0] OM[3:2] M[7:0] MPLLin CLK XTIpll S[1:0] MPLLin UPLL CLK XTOpll HCLK MPLL EXTCLK CLKCNTL PCLK Mpll RTC XTAL CLK FCLK HDIVN PDIVN Control CLKOUT Signal POWCNTL USBCNTL DIVN_UPLL 1/1 or 1/2 Upll P[5:0] M[7:0] UPLL...
Page 213 CLOCK & POWER MANAGEMENT SC32442B RISC MICROPROCESSOR PHASE LOCKED LOOP (PLL) The MPLL within the clock generator, as a circuit, synchronizes an output signal with a reference input signal in frequency and phase. In this application, it includes the following basic blocks as shown in Figure 7-2: the Voltage Controlled Oscillator (VCO) to generate the output frequency proportional to input DC voltage, the divider P to divide the input frequency (Fin) by p, the divider M to divide the VCO output frequency by m which is input to Phase Frequency Detector (PFD), the divider S to divide the VCO output frequency by “s”...
Page 214 SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT Loop Filter Divider PUMP MPLLCAP, UPLLCAP P[5:0] Divider M[7:0] Internal External Divider MPLL,UPLL S[1:0] Figure 7-2. PLL (Phase-Locked Loop) Block Diagram External EXTCLK EXTCLK XTIpll XTIpll XTOpll XTOpll a) X-TAL Oscillation (OM[3:2]=00) b) External Clock Source (OM[3:2]=11) Figure 7-3.
Page 215 CLOCK & POWER MANAGEMENT SC32442B RISC MICROPROCESSOR CLOCK CONTROL LOGIC The Clock Control Logic determines the clock source to be used, i.e., the PLL clock (Mpll) or the direct external clock (XTIpll or EXTCLK). When PLL is configured to a new frequency value, the clock control logic disables the FCLK until the PLL output is stabilized using the PLL locking time.
Page 216 SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT Change PLL Settings In Normal Operation Mode During the operation of the SC32442B in NORMAL mode, the user can change the frequency by writing the PMS value and the PLL lock time will be automatically inserted. During the lock time, the clock is not supplied to the internal blocks in the SC32442B.
Page 217 CLOCK & POWER MANAGEMENT SC32442B RISC MICROPROCESSOR FCLK, HCLK, and PCLK FCLK is used by ARM920T. HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and USB host block. PCLK is used for APB bus, which is used by the peripherals such as WDT, IIS, I2C, PWM timer, MMC interface, ADC, UART, GPIO, RTC and SPI.
Page 218 SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT NOTE 1. CLKDIVN should be set carefully not to exceed the limit of HCLK and PCLK. 2. If HDIVN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous bus mode using following instructions(SC32442 does not support synchronous bus mode).
Page 219 CLOCK & POWER MANAGEMENT SC32442B RISC MICROPROCESSOR POWER MANAGEMENT The Power Management block controls the system clocks by software for the reduction of power consumption in the SC32442B. These schemes are related to PLL, clock control logics (FCLK, HCLK, and PCLK) and wakeup signals.
Page 220 SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT IDLE_BIT=1 IDLE Interrupts, EINT[0:23], RTC alarm STOP / Deep-STOP RESET EINT[15:0], RTC alarm, STOP BIT=1 NORMAL TICK time (SLOW_BIT=0) EINT[15:0], RTC alarm SLOW (SLOW_BIT=1) SLEEP BIT=1 SLEEP Figure 7-8. Power Management State Diagram Table 7-2.
Page 221 CLOCK & POWER MANAGEMENT SC32442B RISC MICROPROCESSOR NORMAL Mode In Normal mode, all peripherals and the basic blocks including power management block, the CPU core, the bus controller, the memory controller, the interrupt controller, DMA, and the external master may operate completely. But, the clock to each peripheral, except the basic blocks, can be stopped selectively by software to reduce the power consumption.
Page 222 SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT Users can change the frequency by enabling SLOW mode bit in CLKSLOW register in PLL on state. The SLOW clock is generated during the SLOW mode. Figure 7-11(Please check the figure correctly) shows the timing diagram.
Page 223 CLOCK & POWER MANAGEMENT SC32442B RISC MICROPROCESSOR If the user switches from SLOW mode to Normal mode by disabling SLOW_BIT and MPLL_OFF bit simultaneously in the CLKSLOW register, the frequency is changed just after the PLL lock time. Figure 7-13 (Please check for the figure number correctly) shows the timing diagram.
Page 224 SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT STOP Mode In STOP mode, all clocks are stopped for minimum power consumption. Therefore, the PLL and oscillator circuit are also stopped. Just after exiting the STOP mode, only NORMAL mode is available. In Figure 7-13-1, the user must return from STOP mode to NORMAL mode.
Page 225 CLOCK & POWER MANAGEMENT SC32442B RISC MICROPROCESSOR Deep-STOP Mode In Deep-STOP mode, Arm920T block is power off and all clocks of internal and pll are stopped for minimum power consumption. Therefore, the PLL and oscillator circuit are also stopped. Just after exiting the Deep-STOP mode, only NORMAL mode is available.
Page 226 SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT SLEEP Mode The block disconnects the internal power. So, there occurs no power consumption due to CPU and the internal logic except the wake-up logic in this mode. Activating the SLEEP mode requires two independent power sources. One of the two power sources supplies the power for the wake-up logic.
Page 227 CLOCK & POWER MANAGEMENT SC32442B RISC MICROPROCESSOR Follow the Procedure to Wake-up from SLEEP mode 1. The internal reset signal will be asserted if one of the wake-up sources is issued. It’s exactly same with the case of the assertion of the external nRESET pin. This reset duration is determined by the internal 16-bit counter logic and the reset assertion time is calculated as tRST = (65535 / XTAL_frequency).
Page 228 SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT Power Control of VDDi and VDDiarm In SLEEP mode, VDDi, VDDiarm, VDDMPLL and VDDUPLL will be turned off, which is controlled by PWREN pin. If PWREN signal is activated(H), VDDi and VDDiarm are supplied by an external voltage regulator. If PWREN pin is inactive (L), the VDDi and VDDiarm are turned off.
Page 229 CLOCK & POWER MANAGEMENT SC32442B RISC MICROPROCESSOR Signaling EINT[15:0] for Wakeup The SC32442B can be woken up from SLEEP mode only if the following conditions are met. a) Level signals (H or L) or edge signals (rising, falling or both) are asserted on EINTn input pin. b) The EINTn pin has to be configured as EINT in the GPIO control register.
Page 230 SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT Output Port State and SLEEP Mode The output port should have a proper logic level in power off mode, which makes the current consumption minimized. If there is no load on an output port pin, H level is preferred. If output is L, the current will be consumed through the internal parasitic resistance;...
Page 231 CLOCK & POWER MANAGEMENT SC32442B RISC MICROPROCESSOR CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER LOCK TIME COUNT REGISTER (LOCKTIME) Register Address Description Reset Value LOCKTIME 0x4C000000 PLL lock time count register 0xFFFFFFFF LOCKTIME Description Initial State U_LTIME [31:16] UPLL lock time count value for UCLK. 0xFFFF (300uS <...
Page 232 SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT PLL CONTROL REGISTER (MPLLCON & UPLLCON) Register Address Description Reset Value MPLLCON 0x4C000004 MPLL configuration register 0x00096030 UPLLCON 0x4C000008 UPLL configuration register 0x0004d030 PLLCON Description Initial State MDIV [19:12] Main divider control 0x96 / 0x4d PDIV [9:4] Pre-divider control...
Page 233 CLOCK & POWER MANAGEMENT SC32442B RISC MICROPROCESSOR CLOCK CONTROL REGISTER (CLKCON) Register Address Description Reset Value CLKCON 0x4C00000C Clock generator control register 0xFFFFF0 CLKCON Description Initial State Camera [19] Control HCLK into Camera block. 0 = Disable, 1 = Enable [18] Control PCLK into SPI block.
Page 234 SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT CLOCK SLOW CONTROL (CLKSLOW) REGISTER Register Address Description Reset Value CLKSLOW 0x4C000010 Slow clock control register 0x00000004 CLKSLOW Description Initial State UCLK_ON 0: UCLK ON (UPLL is also turned on and the UPLL lock time is inserted automatically.) 1: UCLK OFF (UPLL is also turned off.) Reserved...
Page 235 CLOCK & POWER MANAGEMENT SC32442B RISC MICROPROCESSOR CLOCK DIVIDER CONTROL (CLKDIVN) REGISTER Register Address Description Reset Value CLKDIVN 0x4C000014 Clock divider control register 0x00000000 CLKDIVN Description Initial State DIVN_UPLL UCLK select register(UCLK must be 48MHz for USB) 0: UCLK = UPLL clock 1: UCLK = UPLL clock / 2 Set to 0, when UPLL clock is set as 48Mhz Set to 1.
Page 236 SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT CAMERA CLOCK DIVIDER (CAMDIVN) REGISTER Register Address Description Reset Value CAMDIVN 0x4C000018 Camera clock divider register 0x00000000 CAMDIVN Description Initial State DeepSTOP_EN [16] 0:DeepSTOP_EN is Off. 1:DeepSTOP_EN is ON This bit is valid when CLKCON[0]=1. DVS_EN [12] 0:DVS OFF...
Page 237 SC32442B RISC MICROPROCESSOR OVERVIEW The SC32442B supports four-channel DMA controller located between the system bus and the peripheral bus. Each channel of DMA controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions. In other words, each channel can handle the following four cases: 1) Both source and destination are in the system bus 2) The source is in the system bus while the destination is in the peripheral bus 3) The source is in the peripheral bus while the destination is in the system bus...
Page 238: Dma Operation
SC32442B RISC MICROPROCESSOR DMA REQUEST SOURCES Each channel of the DMA controller can select one of the DMA request source among four DMA sources, if H/W DMA request mode is selected by DCON register. (Note that if S/W request mode is selected, this DMA request sources have no meaning at all.) Table 8-1 shows four DMA sources for each channel.
Page 239 SC32442B RISC MICROPROCESSOR EXTERNAL DMA DREQ/DACK PROTOCOL There are three types of external DMA request/acknowledge protocols (Single service Demand, Single service Handshake and Whole service Handshake mode). Each type defines how the signals like DMA request and acknowledge are related to these protocols. Basic DMA Timing The DMA service means performing paired Reads and Writes cycles during DMA operation, which can make one DMA operation.
Page 240 SC32442B RISC MICROPROCESSOR Demand/Handshake Mode Comparison Demand and Handshake modes are related to the protocol between XnXDREQ and XnXDACK. Figure 8-2 shows the differences between the two modes. At the end of one transfer (Single/Burst transfer), DMA checks the state of double-synched XnXDREQ. Demand mode If XnXDREQ remains asserted, the next transfer starts immediately.
Page 241: Transfer Size
SC32442B RISC MICROPROCESSOR Transfer Size There are two different transfer sizes; unit and Burst 4. DMA holds the bus firmly during the transfer of the chunk of data. Thus, other bus masters cannot get the bus. Burst 4 Transfer Size There will be four sequential Reads and Writes performed in the Burst 4 Transfer respectively.
Page 242 SC32442B RISC MICROPROCESSOR EXAMPLES Single service in Demand Mode with Unit Transfer Size The assertion of XnXDREQ will be a need for every unit transfer (Single service mode). The operation continues while the XnXDREQ is asserted (Demand mode), and one pair of Read and Write (Single transfer size) is performed.
Page 243 SC32442B RISC MICROPROCESSOR DMA SPECIAL REGISTERS Each DMA channel has nine control registers (36 in total since there are four channels for DMA controller). Six of the control registers control the DMA transfer, and other three ones monitor the status of DMA controller. The details of those registers are as follows.
Page 244 SC32442B RISC MICROPROCESSOR DMA INITIAL DESTINATION (DIDST) REGISTER Register Address Description Reset Value DIDST0 0x4B000008 DMA 0 initial destination register 0x00000000 DIDST1 0x4B000048 DMA 1 initial destination register 0x00000000 DIDST2 0x4B000088 DMA 2 initial destination register 0x00000000 DIDST3 0x4B0000B8 DMA 3 initial destination register 0x00000000 DIDSTn Description...
Page 245 SC32442B RISC MICROPROCESSOR DMA CONTROL (DCON) REGISTER Register Address Description Reset Value DCON0 0x4B000010 DMA 0 control register 0x00000000 DCON1 0x4B000050 DMA 1 control register 0x00000000 DCON2 0x4B000090 DMA 2 control register 0x00000000 DCON3 0x4B0000D0 DMA 3 control register 0x00000000 DCONn Description Initial State...
Page 246 SC32442B RISC MICROPROCESSOR DCONn Description Initial State SERVMODE [27] Select the service mode between Single service mode and Whole service mode. 0: Single service mode is selected in which after each atomic transfer (single or burst of length four) DMA stops and waits for another DMA request.
Page 247 SC32442B RISC MICROPROCESSOR DMA STATUS (DSTAT) REGISTER Register Address Description Reset Value DSTAT0 0x4B000014 DMA 0 count register 000000h DSTAT1 0x4B000054 DMA 1 count register 000000h DSTAT2 0x4B000094 DMA 2 count register 000000h DSTAT3 0x4B0000D4 DMA 3 count register 000000h DSTATn Description Initial State...
Page 248 SC32442B RISC MICROPROCESSOR DMA CURRENT SOURCE (DCSRC) REGISTER Register Address Description Reset Value DCSRC0 0x4B000018 DMA 0 current Source Register 0x00000000 DCSRC1 0x4B000058 DMA 1 current Source Register 0x00000000 DCSRC2 0x4B000098 DMA 2 current Source Register 0x00000000 DCSRC3 0x4B0000D8 DMA 3 current Source Register 0x00000000 DCSRCn Description...
Page 249 SC32442B RISC MICROPROCESSOR DMA MASK TRIGGER (DMASKTRIG) REGISTER Register Address Description Reset Value DMASKTRIG0 0x4B000020 DMA 0 mask trigger register DMASKTRIG1 0x4B000060 DMA 1 mask trigger register DMASKTRIG2 0x4B0000A0 DMA 2 mask trigger register DMASKTRIG3 0x4B0000E0 DMA 3 mask trigger register DMASKTRIGn Description Initial State...
Page 250 SC32442B RISC MICROPROCESSOR NOTES 8-14...
Page 251 S3C2442B RISC MICROPROCESSOR I/O PORTS I/O PORTS OVERVIEW S3C2442X has 130 multi-functional input/output port pins and there are eight ports as shown below: - Port A(GPA): 25-output port - Port B(GPB): 11-input/out port - Port C(GPC): 16-input/output port - Port D(GPD): 16-input/output port - Port E(GPE): 16-input/output port - Port F(GPF): 8-input/output port - Port G(GPG): 16-input/output port...
Page 252 I/O PORTS S3C2442B RISC MICROPROCESSOR Table 9-1. S3C2442X Port Configuration(Sheet 1 of 5) Port A Selectable Pin Functions GPA22 Output only nFCE – – GPA21 Output only nRSTOUT – – GPA20 Output only nFRE – – GPA19 Output only nFWE –...
Page 253 S3C2442B RISC MICROPROCESSOR I/O PORTS Table 9-1. S3C2442X Port Configuration(Sheet 2 of 5) Port B Selectable Pin Functions GPB10 Input/output nXDREQ0 – – GPB9 Input/output nXDACK0 – – GPB8 Input/output nXDREQ1 – – GPB7 Input/output nXDACK1 – – GPB6 Input/output nXBREQ –...
Page 254 I/O PORTS S3C2442B RISC MICROPROCESSOR Table 9-1. S3C2442X Port Configuration(Sheet 3 of 5) Port D Selectable Pin Functions GPD15 Input/output VD23 nSS0 – GPD14 Input/output VD22 nSS1 – GPD13 Input/output VD21 – – GPD12 Input/output VD20 – – GPD11 Input/output VD19 –...
Page 255 S3C2442B RISC MICROPROCESSOR I/O PORTS Table 9-1. S3C2442X Port Configuration(Sheet 4 of 5) Port F Selectable Pin Functions GPF7 Input/output EINT7 – – GPF6 Input/output EINT6 – – GPF5 Input/output EINT5 – – GPF4 Input/output EINT4 – – GPF3 Input/output EINT3 –...
Page 256 I/O PORTS S3C2442B RISC MICROPROCESSOR Table 9-1. S3C2442X Port Configuration(Sheet 5 of 5) Port H Selectable Pin Functions GPH10 Input/output CLKOUT1 – – GPH9 Input/output CLKOUT0 nSPICS0 – GPH8 Input/output UEXTCLK – – GPH7 Input/output RXD2 nCTS1 – GPH6 Input/output TXD2 nRTS1 –...
Page 257 S3C2442B RISC MICROPROCESSOR I/O PORTS PORT CONTROL DESCRIPTIONS PORT CONFIGURATION REGISTER (GPACON-GPJCON) In S3C2442X, most of the pins are multiplexed pins. So, It is determined which function is selected for each pins. The PnCON(port control register) determines which function is used for each pin. If PE0 –...
Page 258 I/O PORTS S3C2442B RISC MICROPROCESSOR I/O PORT CONTROL REGISTER PORT A CONTROL REGISTERS(GPACON, GPADAT) Register Address Description Reset Value GPACON 0x56000000 Configures the pins of port A 0xffffff GPADAT 0x56000004 The data register for port A Undef. Reserved 0x56000008 Reserved Undef Reserved 0x5600000c...
Page 259 S3C2442B RISC MICROPROCESSOR I/O PORTS GPADAT Description GPA[24:0] [24:0] When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Note : nRSTOUT = nRESET &...
Page 260 I/O PORTS S3C2442B RISC MICROPROCESSOR PORT B CONTROL REGISTERS(GPBCON, GPBDAT, GPBDN) Register Address Description Reset Value GPBCON 0x56000010 Configures the pins of port B GPBDAT 0x56000014 The data register for port B Undef. GPBDN 0x56000018 pull-down disable register for port B Reserved 0x5600001c PBCON...
Page 261 S3C2442B RISC MICROPROCESSOR I/O PORTS PORT C CONTROL REGISTERS(GPCCON, GPCDAT, GPCDN) Register Address Description Reset Value GPCCON 0x56000020 Configures the pins of port C GPCDAT 0x56000024 The data register for port C Undef. GPCDN 0x56000028 pull-down disable register for port C Reserved 0x5600002c GPCCON...
Page 262 I/O PORTS S3C2442B RISC MICROPROCESSOR GPCDAT Description GPC[15:0] [15:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
Page 263 S3C2442B RISC MICROPROCESSOR I/O PORTS PORT D CONTROL REGISTERS(GPDCON, GPDDAT, GPDDN) Register Address Description Reset Value GPDCON 0x56000030 Configures the pins of port D GPDDAT 0x56000034 The data register for port D Undef. GPDDN 0x56000038 pull-down disable register for port D 0xf000 Reserved 0x5600003c...
Page 264 I/O PORTS S3C2442B RISC MICROPROCESSOR GPDDAT Description GPD[15:0] [15:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
Page 265 S3C2442B RISC MICROPROCESSOR I/O PORTS PORT E CONTROL REGISTERS(GPECON, GPEDAT, GPEDN) Register Address Description Reset Value GPECON 0x56000040 Configures the pins of port E GPEDAT 0x56000044 The data register for port E Undef. GPEDN 0x56000048 pull-down disable register for port E 0x0000 Reserved 0x5600004c...
Page 266 I/O PORTS S3C2442B RISC MICROPROCESSOR GPEDAT Description GPE[15:0] [15:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit.
Page 267 S3C2442B RISC MICROPROCESSOR I/O PORTS PORT F CONTROL REGISTERS(GPFCON, GPFDAT) If GPF0 - GPF7 will be used for wake-up signals at power down mode, the ports will be set in interrupt mode. Register Address Description Reset Value GPFCON 0x56000050 Configures the pins of port F GPFDAT 0x56000054 The data register for port F...
Page 268 I/O PORTS S3C2442B RISC MICROPROCESSOR PORT G CONTROL REGISTERS(GPGCON, GPGDAT) If GPG0 - GPG7 will be used for wake-up signals at Sleep mode, the ports will be set in interrupt mode. Register Address Description Reset Value GPGCON 0x56000060 Configures the pins of port G GPGDAT 0x56000064 The data register for port G...
Page 269 S3C2442B RISC MICROPROCESSOR I/O PORTS GPGDAT Description GPG[15:0] [15:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit.
Page 270 I/O PORTS S3C2442B RISC MICROPROCESSOR PORT H CONTROL REGISTERS(GPHCON, GPHDAT) Register Address Description Reset Value GPHCON 0x56000070 Configures the pins of port H GPHDAT 0x56000074 The data register for port H Undef. GPHDN 0x56000078 pull-down disable register for port H 0x000 Reserved 0x5600007c...
Page 271 S3C2442B RISC MICROPROCESSOR I/O PORTS GPHDAT Description GPH[10:0] [10:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit.
Page 272 I/O PORTS S3C2442B RISC MICROPROCESSOR PORT J CONTROL REGISTERS(GPJCON, GPJDAT) Register Address Description Reset Value GPJCON 0x560000d0 Configures the pins of port J GPJDAT 0x560000d4 The data register for port J Undef. GPJDN 0x560000d8 pull-down disable register for port J 0x0000 Reserved 0x560000dc...
Page 273 S3C2442B RISC MICROPROCESSOR I/O PORTS GPJDAT Description GPJ15:0] [12:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit.
Page 274 I/O PORTS S3C2442B RISC MICROPROCESSOR MISCELLANEOUS control register(MISCCR) In Sleep mode, the data bus(D[31:0] or D[15:0] can be set as Hi-Z and Output ‘0’ state. But, because of the characteristics of IO pad, the data bus pull-down resisters have to be turned on or off to reduce the power consumption.
Page 275 S3C2442B RISC MICROPROCESSOR I/O PORTS CLKSEL1 [10:8] Select source clock with CLKOUT1 pad 000 = MPLL output 001 = UPLL output 010 = RTC clock output 011 = HCLK 100 = PCLK 101 = DCLK1 11x = reserved Reserved CLKSEL0 [6:4] Select source clock with CLKOUT0 pad 000 = MPLL INPUT Clock(XTAL)
Page 276 I/O PORTS S3C2442B RISC MICROPROCESSOR DCLK CONTROL REGISTERS(DCLKCON) Register Address Description Reset Value DCLKCON 0x56000084 DCLK0/1 Control Register DCLKCON Description DCLK1CMP [27:24] DCLK1 Compare value clock toggle value.( < DCLK1DIV) If the DCLK1CMP is n, Low level duration is( n + 1), High level duration is((DCLK1DIV + 1) –( n +1)) DCLK1DIV [23:20]...
Page 277 S3C2442B RISC MICROPROCESSOR I/O PORTS EXTINTn(External Interrupt Control Register n) The 8 external interrupts can be requested by various signaling methods. The EXTINT register configures the signaling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity.
Page 278 I/O PORTS S3C2442B RISC MICROPROCESSOR EXTINT1 Description FLTEN15 [31] Filter Enable for EINT15 0 = Filter Disable 1= Filter Enable EINT15 [30:28] Setting the signaling method of the EINT15. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered FLTEN14...
Page 279 S3C2442B RISC MICROPROCESSOR I/O PORTS EXTINT2 Description Reset Value FLTEN23 [31] Filter Enable for EINT23 0 = Filter Disable 1= Filter Enable EINT23 [30:28] Setting the signaling method of the EINT23. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered FLTEN22...
Page 280 I/O PORTS S3C2442B RISC MICROPROCESSOR EINT17 [6:4] Setting the signaling method of the EINT17. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered FLTEN16 Filter Enable for EINT16 0 = Filter Disable 1= Filter Enable EINT16...
Page 281 S3C2442B RISC MICROPROCESSOR I/O PORTS EINTFLTn(External Interrupt Filter Register n) To recognize the level interrupt, the valid logic level on EXTINTn pin must be retained for 40ns at least because of the noise filter. Register Address Description Reset Value EINTFLT0 0x56000094 reserved 0x000000...
Page 282 I/O PORTS S3C2442B RISC MICROPROCESSOR EINTMASK(External Interrupt Mask Register) Register Address Description Reset Value EINTMASK 0x560000a4 External interupt mask Register 0x000fffff EINTMASK Description EINT23 [23] 0 = enable interrupt 1= masked EINT22 [22] 0 = enable interrupt 1= masked EINT21 [21] 0 = enable interrupt 1= masked...
Page 283 S3C2442B RISC MICROPROCESSOR I/O PORTS EINTPEND(External Interrupt Pending Register) Register Address Description Reset Value EINTPEND 0x560000a8 External interupt pending Register 0x00 EINTPEND Description Reset Value EINT23 [23] It is cleard by writing “1” 0 = not occur 1= occur interrupt EINT22 [22] It is cleard by writing “1”...
Page 284 I/O PORTS S3C2442B RISC MICROPROCESSOR EINT5 It is cleard by writing “1” 0 = not occur 1= occur interrupt EINT4 It is cleard by writing “1” 0 = not occur 1= occur interrupt Reserved [3:0] Reserved 0000 9-34...
Page 285 S3C2442B RISC MICROPROCESSOR I/O PORTS GSTATUSn (General Status Registers) Register Address Description Reset Value GSTATUS0 0x560000ac External pin status Not define GSTATUS1 0x560000b0 Chip ID 0x32440001 GSTATUS2 0x560000b4 Reset Status GSTATUS3 0x560000b8 Inform register GSTATUS4 0x560000bc Inform register GSTATUS0 Description nWAIT Status of nWAIT pin NCON...
Page 286 I/O PORTS S3C2442B RISC MICROPROCESSOR DSCn (Drive Strength Control) Control the Memory I/O drive strength Register Address Description Reset Value DSC0 0x560000c4 strength control register 0 DSC1 0x560000c8 strength control register 1 DSC0 Description Reset Value nEN_DSC [31] enable Drive Strength Control 0: enable 1: Disable Reserved...
Page 287 S3C2442B RISC MICROPROCESSOR I/O PORTS DSC1 Description Reset Value DSC_SCK1 [29:28] SCLK1 Drive strength. 00: 12mA 10: 10mA 01: 8mA 11: 6mA DSC_SCK0 [27:26] SCLK0 Drive strength. 00: 12mA 10: 10mA 01: 8mA 11: 6mA DSC_SCKE [25:24] SCKE Drive strength. 00: 10mA 10: 8mA 01: 6mA...
Page 288 I/O PORTS S3C2442B RISC MICROPROCESSOR MSLCON (Memory Sleep Control Register) Select memory interface status when in SLEEP mode. Register Address Description Reset Value MSLCON 0x560000cc Memory Sleep Control Register MSLCON Description Reset Value PSC_DATA [11] DATA[31:0] pin status in Sleep mode. 0: Hi-Z 1: Output “0”.
Page 289 SC32442B RISC MICROPROCESSOR PWM TIMER PWM TIMER OVERVIEW The SC32442B has five 16-bit timers. Timer 0, 1, 2, and 3 have Pulse Width Modulation (PWM) function. Timer 4 has an internal timer only with no output pins. The timer 0 has a dead-zone generator, which is used with a large current device.
Page 290 PWM TIMER SC32442B RISC MICROPROCESSOR TCMPB0 TCNTB0 TOUT0 Dead Zone Generator Dead Zone Control Logic0 PCLK 8-Bit TCMPB1 TCNTB1 Prescaler 1/16 TOUT1 TCLK0 Control Clock Logic1 Divider Dead Zone TCMPB2 TCNTB2 TOUT2 Control Logic2 8-Bit TCMPB3 TCNTB3 Prescaler 1/16 TCLK1 TOUT3 Control Clock...
Page 291 SC32442B RISC MICROPROCESSOR PWM TIMER PWM TIMER OPERATION PRESCALER & DIVIDER An 8-bit prescaler and a 4-bit divider make the following output frequencies: 4-bit divider settings Minimum resolution Maximum resolution Maximum interval (prescaler = 0) (prescaler = 255) (TCNTBn = 65535) 1/2 (PCLK = 50 MHz) 0.0400 us (25.0000 MHz) 10.2400 us (97.6562 KHz)
Page 292 PWM TIMER SC32442B RISC MICROPROCESSOR AUTO RELOAD & DOUBLE BUFFERING SC32442B PWM Timers have a double buffering function, enabling the reload value changed for the next timer operation without stopping the current timer operation. So, although the new timer value is set, a current timer operation is completed successfully.
Page 293 SC32442B RISC MICROPROCESSOR PWM TIMER TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT An auto reload operation of the timer occurs when the down counter reaches 0. So, a starting value of the TCNTn has to be defined by the user in advance. In this case, the starting value has to be loaded by the manual update bit.
Page 294 PWM TIMER SC32442B RISC MICROPROCESSOR TIMER OPERATION TOUTn Figure 10-4. Example of a Timer Operation The above Figure 10-4 shows the result of the following procedure: 1. Enable the auto re-load function. Set the TCNTBn to 160 (50+110) and the TCMPBn to 110. Set the manual update bit and configure the inverter bit (on/off).
Page 295 SC32442B RISC MICROPROCESSOR PWM TIMER PULSE WIDTH MODULATION (PWM) Write Write Write TCMPBn = 60 TCMPBn = 40 TCMPBn = 30 Write Write Write TCMPBn = 50 TCMPBn = 30 TCMPBn = Next PWM Value Figure 10-5. Example of PWM PWM function can be implemented by using the TCMPBn.
Page 296 PWM TIMER SC32442B RISC MICROPROCESSOR OUTPUT LEVEL CONTROL Inverter off Inverter on Initial State Period 1 Period 2 Timer Stop Figure 10-6. Inverter On/Off The following procedure describes how to maintain TOUT as high or low (assume the inverter is off): 1.
Page 297 SC32442B RISC MICROPROCESSOR PWM TIMER DEAD ZONE GENERATOR The Dead Zone is for the PWM control in a power device. This function enables the insertion of the time gap between a turn-off of a switching device and a turn on of another switching device. This time gap prohibits the two switching devices from being turned on simultaneously, even for a very short time.
Page 298 PWM TIMER SC32442B RISC MICROPROCESSOR DMA REQUEST MODE The PWM timer can generate a DMA request at every specific time. The timer keeps DMA request signals (nDMA_REQ) low until the timer receives an ACK signal. When the timer receives the ACK signal, it makes the request signal inactive.
Page 299 SC32442B RISC MICROPROCESSOR PWM TIMER PWM TIMER CONTROL REGISTERS TIMER CONFIGURATION REGISTER0 (TCFG0) Timer input clock Frequency = PCLK / {prescaler value+1} / {divider value} {prescaler value} = 0~255 {divider value} = 2, 4, 8, 16 Register Address Description Reset Value TCFG0 0x51000000 Configures the two 8-bit prescalers...
Page 300 PWM TIMER SC32442B RISC MICROPROCESSOR TIMER CONFIGURATION REGISTER1 (TCFG1) Register Address Description Reset Value TCFG1 0x51000004 5-MUX & DMA mode selecton register 0x00000000 TCFG1 Description Initial State Reserved [31:24] 00000000 DMA mode [23:20] Select DMA request channel 0000 0000 = No select (all interrupt) 0001 = Timer0 0010 = Timer1 0011 = Timer2 0100 = Timer3...
Page 301 SC32442B RISC MICROPROCESSOR PWM TIMER TIMER CONTROL (TCON) REGISTER Register Address Description Reset Value TCON 0x51000008 Timer control register 0x00000000 TCON Description Initial state Timer 4 auto reload on/off [22] Determine auto reload on/off for Timer 4. 0 = One-shot 1 = Interval mode (auto reload) (note) [21]...
Page 302 PWM TIMER SC32442B RISC MICROPROCESSOR TCON (Continued) TCON Description Initial state Reserved [7:5] Reserved Dead zone enable Determine the dead zone operation. 0 = Disable 1 = Enable Timer 0 auto reload on/off Determine auto reload on/off for Timer 0. 0 = One-shot 1 = Interval mode(auto reload) Timer 0 output inverter on/off...
Page 303 SC32442B RISC MICROPROCESSOR PWM TIMER TIMER 0 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB0/TCMPB0) Register Address Description Reset Value TCNTB0 0x5100000C Timer 0 count buffer register 0x00000000 TCMPB0 0x51000010 Timer 0 compare buffer register 0x00000000 TCMPB0 Description Initial State Timer 0 compare buffer register [15:0] Set compare buffer value for Timer 0...
Page 304 PWM TIMER SC32442B RISC MICROPROCESSOR TIMER 1 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB1/TCMPB1) Register Address Description Reset Value TCNTB1 0x51000018 Timer 1 count buffer register 0x00000000 TCMPB1 0x5100001C Timer 1 compare buffer register 0x00000000 TCMPB1 Description Initial State Timer 1 compare buffer register [15:0] Set compare buffer value for Timer 1...
Page 305 SC32442B RISC MICROPROCESSOR PWM TIMER TIMER 2 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB2/TCMPB2) Register Address Description Reset Value TCNTB2 0x51000024 Timer 2 count buffer register 0x00000000 TCMPB2 0x51000028 Timer 2 compare buffer register 0x00000000 TCMPB2 Description Initial State Timer 2 compare buffer register [15:0] Set compare buffer value for Timer 2...
Page 306 PWM TIMER SC32442B RISC MICROPROCESSOR TIMER 3 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB3/TCMPB3) Register Address Description Reset Value TCNTB3 0x51000030 Timer 3 count buffer register 0x00000000 TCMPB3 0x51000034 Timer 3 compare buffer register 0x00000000 TCMPB3 Description Initial State Timer 3 compare buffer register [15:0] Set compare buffer value for Timer 3...
Page 307 SC32442B RISC MICROPROCESSOR PWM TIMER TIMER 4 COUNT BUFFER REGISTER (TCNTB4) Register Address Description Reset Value TCNTB4 0x5100003C Timer 4 count buffer register 0x00000000 TCNTB4 Description Initial State Timer 4 count buffer register [15:0] Set count buffer value for Timer 4 0x00000000 TIMER 4 COUNT OBSERVATION REGISTER (TCNTO4) Register...
Page 308 PWM TIMER SC32442B RISC MICROPROCESSOR NOTES 10-20...
Page 309 SC32442B RISC MICROPROCESSOR UART UART OVERVIEW The SC32442B Universal Asynchronous Receiver and Transmitter (UART) provide three independent asynchronous serial I/O (SIO) ports, each of which can operate in Interrupt-based or DMA-based mode. In other words, the UART can generate an interrupt or a DMA request to transfer data between CPU and the UART. The UART can support bit rates up to 115.2K bps using system clock.
Page 310 UART SC32442B RISC MICROPROCESSOR BLOCK DIAGRAM P e r ip h e r a l B U S T r a n s m it t e r T r a n s m it F IF O R e g is te r ( F IF O m o d e ) T r a n s m it B u ffe r R e g is te r ( 6 4 B y te )
Page 311 SC32442B RISC MICROPROCESSOR UART UART OPERATION The following sections describe the UART operations that include data transmission, data reception, interrupt generation, baud-rate generation, Loopback mode, Infrared mode, and auto flow control. Data Transmission The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register (ULCONn).
Page 312 UART SC32442B RISC MICROPROCESSOR Auto Flow Control (AFC) The SC32442B's UART 0 and UART 1 support auto flow control with nRTS and nCTS signals. In case, it can be connected to external UARTs. If users want to connect a UART to a Modem, disable auto flow control bit in UMCONn register and control the signal of nRTS by software.
Page 313 SC32442B RISC MICROPROCESSOR UART RS-232C interface If the user wants to connect the UART to modem interface (instead of null modem), nRTS, nCTS, nDSR, nDTR, DCD and nRI signals are needed. In this case, the users can control these signals with general I/O ports by software because the AFC does not support the RS-232C interface.
Page 314 UART SC32442B RISC MICROPROCESSOR UART Error Status FIFO UART has the error status FIFO besides the Rx FIFO register. The error status FIFO indicates which data, among FIFO registers, is received with an error. The error interrupt will be issued only when the data, which has an error, is ready to read out.
Page 315 SC32442B RISC MICROPROCESSOR UART Baud-rate Generation Each UART's baud-rate generator provides the serial clock for the transmitter and the receiver. The source clock for the baud-rate generator can be selected with the SC32442B's internal system clock or UEXTCLK. In other words, dividend is selectable by setting Clock Selection of UCONn.
Page 316 UART SC32442B RISC MICROPROCESSOR Infrared (IR) Mode The SC32442B UART block supports infrared (IR) transmission and reception, which can be selected by setting the Infrared-mode bit in the UART line control register (ULCONn). Figure 11-4 illustrates how to implement the IR mode.
Page 317 SC32442B RISC MICROPROCESSOR UART SIO Frame Data Bits Start Stop Figure 11-4. Serial I/O Frame Timing Diagram (Normal UART) IR Transmit Frame Data Bits Start Stop Pulse Width = 3/16 Bit Frame Time Figure 11-5. Infrared Transmit Mode Frame Timing Diagram IR Receive Frame Data Bits Start...
Page 318 UART SC32442B RISC MICROPROCESSOR UART SPECIAL REGISTERS UART LINE CONTROL REGISTER There are three UART line control registers including ULCON0, ULCON1, and ULCON2 in the UART block. Register Address Description Reset Value ULCON0 0x50000000 UART channel 0 line control register 0x00 ULCON1 0x50004000...
Page 319 SC32442B RISC MICROPROCESSOR UART UART CONTROL REGISTER There are three UART control registers including UCON0, UCON1 and UCON2 in the UART block. Register Address Description Reset Value UCON0 0x50000004 UART channel 0 control register 0x00 UCON1 0x50004004 UART channel 1 control register 0x00 UCON2 0x50008004...
Page 320 UART SC32442B RISC MICROPROCESSOR Tx Interrupt Type Interrupt request type. 0 = Pulse (Interrupt is requested as soon as the Tx buffer becomes empty in Non-FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode.) 1 = Level (Interrupt is requested while Tx buffer is empty in Non- FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode.) Rx Interrupt Interrupt request type.
Page 321 SC32442B RISC MICROPROCESSOR UART UART CONTROL REGISTER (Continued) Transmit Mode [3:2] Determine which function is currently able to write Tx data to the UART transmit buffer register. (UART Tx Enable/Disable) 00 = Disable 01 = Interrupt request or polling mode 10 = DMA0 request (Only for UART0), DMA3 request (Only for UART2) 11 = DMA1 request (Only for UART1)
Page 322 UART SC32442B RISC MICROPROCESSOR UART FIFO CONTROL REGISTER There are three UART FIFO control registers including UFCON0, UFCON1 and UFCON2 in the UART block. Register Address Description Reset Value UFCON0 0x50000008 UART channel 0 FIFO control register UFCON1 0x50004008 UART channel 1 FIFO control register UFCON2 0x50008008 UART channel 2 FIFO control register...
Page 323 SC32442B RISC MICROPROCESSOR UART UART MODEM CONTROL REGISTER There are two UART MODEM control registers including UMCON0 and UMCON1 in the UART block. Register Address Description Reset Value UMCON0 0x5000000C UART channel 0 Modem control register UMCON1 0x5000400C UART channel 1 Modem control register Reserved 0x5000800C Reserved...
Page 324 UART SC32442B RISC MICROPROCESSOR UART TX/RX STATUS REGISTER There are three UART Tx/Rx status registers including UTRSTAT0, UTRSTAT1 and UTRSTAT2 in the UART block. Register Address Description Reset Value UTRSTAT0 0x50000010 UART channel 0 Tx/Rx status register UTRSTAT1 0x50004010 UART channel 1 Tx/Rx status register UTRSTAT2 0x50008010 UART channel 2 Tx/Rx status register...
Page 325 SC32442B RISC MICROPROCESSOR UART UART ERROR STATUS REGISTER There are three UART Rx error status registers including UERSTAT0, UERSTAT1 and UERSTAT2 in the UART block. Register Address Description Reset Value UERSTAT0 0x50000014 UART channel 0 Rx error status register UERSTAT1 0x50004014 UART channel 1 Rx error status register UERSTAT2...
Page 326 UART SC32442B RISC MICROPROCESSOR UART FIFO STATUS REGISTER There are three UART FIFO status registers including UFSTAT0, UFSTAT1 and UFSTAT2 in the UART block. Register Address Description Reset Value UFSTAT0 0x50000018 UART channel 0 FIFO status register 0x00 UFSTAT1 0x50004018 UART channel 1 FIFO status register 0x00 UFSTAT2...
Page 327 SC32442B RISC MICROPROCESSOR UART UART MODEM STATUS REGISTER There are two UART modem status registers including UMSTAT0, UMSTAT1 in the UART block. Register Address Description Reset Value UMSTAT0 0x5000001C UART channel 0 Modem status register UMSTAT1 0x5000401C UART channel 1 Modem status register Reserved 0x5000801C Reserved...
Page 328 UART SC32442B RISC MICROPROCESSOR UART TRANSMIT BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) There are three UART transmit buffer registers including UTXH0, UTXH1 and UTXH2 in the UART block. UTXHn has an 8-bit data for transmission data. Register Address Description Reset Value UTXH0 0x50000020(L)
Page 329 SC32442B RISC MICROPROCESSOR UART UART BAUD RATE DIVISOR REGISTER There are three UART baud rate divisor registers including UBRDIV0, UBRDIV1 and UBRDIV2 in the UART block. The value stored in the baud rate divisor register (UBRDIVn), is used to determine the serial Tx/Rx clock rate (baud rate) as follows: UBRDIVn = (int)( UART clock / ( buad rate x 16) ) –1...
Page 330 UART SC32442B RISC MICROPROCESSOR NOTES 11-22...
Page 331 SC32442B RISC MICROPROCESSOR USB HOST USB HOST CONTROLLER OVERVIEW SC32442B supports 2-port USB host interface as follows: • OHCI Rev 1.0 compatible • USB Rev1.1 compatible • Two down stream ports • Support for both LowSpeed and FullSpeed USB devices •...
Page 332 USB HOST SC32442B RISC MICROPROCESSOR USB HOST CONTROLLER SPECIAL REGISTERS The SC32442B USB host controller complies with OHCI Rev 1.0. Refer to Open Host Controller Interface Rev 1.0 specification for detailed information. OHCI REGISTERS FOR USB HOST CONTROLLER Register Base Address Description Reset Value HcRevision...
Page 333: Usb Device Controller
SC32442B RISC MICROPROCESSOR USB DEVICE USB DEVICE CONTROLLER OVERVIEW Universal Serial Bus (USB) device controller is designed to provide a high performance full speed function controller solution with DMA interface. USB device controller allows bulk transfer with DMA, interrupt transfer and control transfer.
Page 334 USB DEVICE SC32442B RISC MICROPROCESSOR MC_ADDR[13:0] MC_DATA_IN[31:0] RT_VM_IN MC_DATA_OUT[31:0] RT_VP_IN USB_CLK SYS_CLK SYS_RESETN RT_VP_OUT & MC_WR RT_VM_OUT WR_RDN RT_UX_OEN MC_CSN MC_INTR RT_UXSUSPEND DREQN[3:0] DACKN[3:0] FIFOs Figure 13-1. USB Device Controller Block Diagram 13-2...
Page 335: Table Of Contents
SC32442B RISC MICROPROCESSOR USB DEVICE USB DEVICE CONTROLLER SPECIAL REGISTERS This section describes detailed functionalities about register sets device controller. All special function register is byte-accessible or word-accessible. If you access byte mode offset-address is different in little endian and big endian. All reserved bit is zero. Common indexed registers depend on INDEX register (INDEX_REG) (offset address: 0X178) value.
Page 336 USB DEVICE SC32442B RISC MICROPROCESSOR EP2_DMA_CON Endpoint2 DMA control register 0x218(L) / 0x21B(B) EP2_DMA_UNIT Endpoint2 DMA unit counter register 0x21C(L) / 0x21F(B) EP2_DMA_FIFO Endpoint2 DMA FIFO counter register 0x220(L) / 0x223(B) EP2_DMA_TTC_L Endpoint2 DMA transfer counter low-byte register 0x224(L) / 0x227(B) EP2_DMA_TTC_M Endpoint2 DMA transfer counter middle-byte register 0x228(L) / 0x22B(B)
Page 337: Func_Addr_Reg
SC32442B RISC MICROPROCESSOR USB DEVICE FUNCTION ADDRESS REGISTER (FUNC_ADDR_REG) This register maintains the USB device controller address assigned by the host. The Micro Controller Unit (MCU) writes the value received through a SET_ADDRESS descriptor to this register. This address is used for the next token.
Page 338: Pwr_Reg
USB DEVICE SC32442B RISC MICROPROCESSOR POWER MANAGEMENT REGISTER (PWR_REG) This register acts as a power control register in the USB block. Register Address Description Reset Value PWR_REG 0x52000144(L) Power management register 0x00 0x52000147(B) (byte) PWR_ADDR Description Initial State Reserved [7:4] USB_RESET Set by the USB if reset signaling is received from the host.
Page 339: Ep_Int_Reg (Ep0-Ep4)
SC32442B RISC MICROPROCESSOR USB DEVICE INTERRUPT REGISTER (EP_INT_REG/USB_INT_REG) The USB core has two interrupt registers. These registers act as status registers for the MCU when it is interrupted. The bits are cleared by writing a ‘1’ (not ‘0’) to each bit that was set. Once the MCU is interrupted, MCU should read the contents of interrupt-related registers and write back to clear the contents if it is necessary.
Page 340: Usb_Int_Reg
USB DEVICE SC32442B RISC MICROPROCESSOR Register Address Description Reset Value USB_INT_REG 0x52000158(L) USB interrupt pending/clear register 0x00 0x5200015B(B) (byte) USB_INT_REG Description Initial State RESET Set by the USB when it receives reset signaling. Interrupt /CLEAR Set by the USB when it receives resume signaling, while RESUME in Suspend mode.
Page 341: Ep_Int_En_Reg (Ep0-Ep4)
SC32442B RISC MICROPROCESSOR USB DEVICE INTERRUPT ENABLE REGISTER (EP_INT_EN_REG/USB_INT_EN_REG) Corresponding to each interrupt register, The USB device controller also has two interrupt enable registers (except resume interrupt enable). By default, usb reset interrupt is enabled. If bit = 0, the interrupt is disabled. If bit = 1, the interrupt is enabled.
Page 342: Usb_Int_En_Reg
USB DEVICE SC32442B RISC MICROPROCESSOR Register Address Description Reset Value USB_INT_EN_REG 0x520016C(L) Determine which interrupt is enabled 0x04 0x5200016F(B) (byte) INT_MASK_REG Description Initial State RESET_INT_EN Reset interrupt enable bit 0 = Interrupt disable 1 = Enable Reserved SUSPEND_INT_EN Suspend interrupt enable bit 0 = Interrupt disable 1 = Enable 13-10...
Page 343: Frame_Num1_Reg
SC32442B RISC MICROPROCESSOR USB DEVICE FRAME NUMBER REGISTER (FPAME_NUM1_REG/FRAME_NUM2_REG) When the host transfers USB packets, each Start Of Frame (SOF) packet includes a frame number. The USB device controller catches this frame number and loads it into this register automatically. Register Address Description...
Page 344 USB DEVICE SC32442B RISC MICROPROCESSOR INDEX REGISTER (INDEX_REG) The INDEX register is used to indicate certain endpoint registers effectively. The MCU can access the endpoint registers (MAXP_REG, IN_CSR1_REG, IN_CSR2_REG, OUT_CSR1_REG, OUT_CSR2_REG, OUT_FIFO_CNT1_REG, and OUT_FIFO_CNT2_REG) for an endpoint inside the core using the INDEX register. Register Address Description...
Page 345 SC32442B RISC MICROPROCESSOR USB DEVICE END POINT0 CONTROL STATUS REGISTER (EP0_CSR) This register has the control and status bits for Endpoint 0. Since a control transaction is involved with both IN and OUT tokens, there is only one CSR register, mapped to the IN CSR1 register. (Share IN1_CSR and can access by writing index register “0”...
Page 346 USB DEVICE SC32442B RISC MICROPROCESSOR END POINT IN CONTROL STATUS REGISTER (IN_CSR1_REG/IN_CSR2_REG) Register Address Description Reset Value IN_CSR1_REG 0x52000184(L) IN END POINT control status register1 0x00 0x52000187(B) (byte) IN_CSR1_REG Description Initial State Reserved CLR_DATA_ Used in Set-up procedure. TOGGLE CLEAR 0: There are alternation of DATA0 and DATA1 1: The data toggle bit is cleared and PID in packet will maintain DATA0...
Page 347: In_Csr2_Reg
SC32442B RISC MICROPROCESSOR USB DEVICE Register Address Description Reset Value IN_CSR2_REG 0x52000188(L) IN END POINT control status register2 0x20 0x5200018B(B) (byte) IN_CSR2_REG Description Initial State AUTO_SET If set, whenever the MCU writes MAXP data, IN_PKT_RDY will automatically be set by the core without any intervention from MCU.
Page 348: Out_Csr1_Reg
USB DEVICE SC32442B RISC MICROPROCESSOR END POINT OUT CONTROL STATUS REGISTER (OUT_CSR1_REG/OUT_CSR2_REG) Register Address Description Reset Value OUT_CSR1_REG 0x52000190(L) End Point out control status register1 0x00 (byte) 0x52000193(B) OUT_CSR1_REG Description Initial State CLR_DATA_TOGGLE CLEAR When the MCU writes a 1 to this bit, the data toggle sequence bit is reset to DATA0.
Page 349: Out_Csr2_Reg
SC32442B RISC MICROPROCESSOR USB DEVICE Register Address Description Reset Value OUT_CSR2_REG 0x52000194(L) End Point out control status register2 0x00 (byte) 0x52000197(B) OUT_CSR2_REG Description Initial State AUTO_CLR If the MCU is set, whenever the MCU reads data from the OUT FIFO, OUT_PKT_RDY will automatically be cleared by the logic without any intervention from the MCU.
Page 350: Out_Fifo_Cnt1_Reg
USB DEVICE SC32442B RISC MICROPROCESSOR END POINT OUT WRITE COUNT REGISTER (OUT_FIFO_CNT1_REG/OUT_FIFO_CNT2_REG) These registers maintain the number of bytes in the packet as the number is unloaded by the MCU. Register Address Description Reset Value OUT_FIFO_CNT1_REG 0x52000198(L) End Point out write count register1 0x00 0x5200019B(B) (byte)
Page 351 SC32442B RISC MICROPROCESSOR USB DEVICE DMA INTERFACE CONTROL REGISTER (EPN_DMA_CON) Register Address Description Reset Value EP1_DMA_CON 0x52000200(L) EP1 DMA interface control register 0x00 0x52000203(B) (byte) EP2_DMA_CON 0x52000218(L) EP2 DMA interface control register 0x00 0x5200021B(B) (byte) EP3_DMA_CON 0x52000240(L) EP3 DMA interface control register 0x00 0x52000243(B) (byte)
Page 352 USB DEVICE SC32442B RISC MICROPROCESSOR DMA UNIT COUNTER REGISTER (EPN_DMA_UNIT) This register is valid in Demand mode. In other modes, this register value must be set to ‘0x01’ Register Address Description Reset Value EP1_DMA_UNIT 0x52000204(L) EP1 DMA transfer unit counter base register 0x00 0x52000207(B) (byte)
Page 353 SC32442B RISC MICROPROCESSOR USB DEVICE DMA FIFO COUNTER REGISTER (EPN_DMA_FIFO) This register has values in byte size in FIFO to be transferred by DMA. In case of OUT_DMA_RUN enabled, the value in OUT FIFO Write Count Register1 will be loaded in this register automatically. In case of IN DMA mode, the MCU should set proper value by software.
Page 354 USB DEVICE SC32442B RISC MICROPROCESSOR DMA TOTAL TRANSFER COUNTER REGISTER (EPn_DMA_TTC_L,M,H) This register should have total number of bytes to be transferred using DMA (total 20-bit counter). Register Address Description Reset Value EP1_DMA_TTC_L 0x5200020C(L) EP1 DMA total transfer counter(lower byte) 0x00 0x5200020F(B) (byte)
Page 355: Interrupt Controller
SC32442B RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT CONTROLLER OVERVIEW The interrupt controller in the SC32442B receives the request from 60 interrupt sources. These interrupt sources are provided by internal peripherals such as DMA controller, UART, IIC, and others. In these interrupt sources, the UARTn, EINTn interrupts are 'OR'ed to the interrupt controller.
Page 356 INTERRUPT CONTROLLER SC32442B RISC MICROPROCESSOR INTERRUPT CONTROLLER OPERATION F-bit and I-bit of Program Status Register (PSR) If the F-bit of PSR in ARM920T CPU is set to 1, the CPU does not accept the Fast Interrupt Request (FIQ) from the interrupt controller. Likewise, If I-bit of the PSR is set to 1, the CPU does not accept the Interrupt Request (IRQ) from the interrupt controller.
Page 357 SC32442B RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT SOURCES The interrupt controller supports 60 interrupt sources as shown in the table below. Sources Descriptions Arbiter Group INT_ADC ADC EOC and Touch interrupt (INT_ADC_S/INT_TC) ARB5 INT_RTC RTC alarm interrupt ARB5 INT_SPI1 SPI1 interrupt ARB5 INT_UART0 UART0 Interrupt (ERR, RXD, and TXD)
Page 358 INTERRUPT CONTROLLER SC32442B RISC MICROPROCESSOR INTERRUPT SUB SOURCES Sub Sources Descriptions Source INT_CAM_P P-port capture interrupt in camera interface INT_CAM INT_CAM_C C-port capture interrupt in camera interface INT_CAM INT_ADC_S ADC interrupt INT_ADC INT_TC Touch screen interrupt (pen up/down) INT_ADC INT_ERR2 UART2 error interrupt INT_UART2 INT_TXD2...
Page 359 SC32442B RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and one second-level arbiter as shown in Figure 14-1 below. REQ1/EINT0 REQ2/EINT1 REQ0 ARBITER0 REQ3/EINT2 REQ1 REQ4/EINT3...
Page 360 INTERRUPT CONTROLLER SC32442B RISC MICROPROCESSOR INTERRUPT PRIORITY Each arbiter can handle six interrupt requests based on the one bit arbiter mode control (ARB_MODE) and two bits of selection control signals (ARB_SEL) as follows: If ARB_SEL bits are 00b, the priority order is REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5. If ARB_SEL bits are 01b, the priority order is REQ0, REQ2, REQ3, REQ4, REQ1, and REQ5.
Page 361 SC32442B RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT CONTROLLER SPECIAL REGISTERS There are five control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, and interrupt pending register. All the interrupt requests from the interrupt sources are first registered in the source pending register. They are divided into two groups including Fast Interrupt Request (FIQ) and Interrupt Request (IRQ), based on the interrupt mode register.
Page 362 INTERRUPT CONTROLLER SC32442B RISC MICROPROCESSOR SRCPND Description Initial State INT_ADC [31] 0 = Not requested, 1 = Requested INT_RTC [30] 0 = Not requested, 1 = Requested INT_SPI1 [29] 0 = Not requested, 1 = Requested INT_UART0 [28] 0 = Not requested, 1 = Requested INT_IIC [27]...
Page 363 SC32442B RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT MODE (INTMOD) REGISTER This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode. Otherwise, it is processed in the IRQ mode (normal interrupt).
Page 364 INTERRUPT CONTROLLER SC32442B RISC MICROPROCESSOR INTMOD Description Initial State INT_ADC [31] 0 = IRQ, 1 = FIQ INT_RTC [30] 0 = IRQ, 1 = FIQ INT_SPI1 [29] 0 = IRQ, 1 = FIQ INT_UART0 [28] 0 = IRQ, 1 = FIQ INT_IIC [27] 0 = IRQ,...
Page 365 SC32442B RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT MASK (INTMSK) REGISTER This register also has 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the CPU does not service the interrupt request from the corresponding interrupt source (note that even in such a case, the corresponding bit of SRCPND register is set to 1).
Page 366 INTERRUPT CONTROLLER SC32442B RISC MICROPROCESSOR INTMSK Description Initial State INT_ADC [31] 0 = Service available, 1 = Masked INT_RTC [30] 0 = Service available, 1 = Masked INT_SPI1 [29] 0 = Service available, 1 = Masked INT_UART0 [28] 0 = Service available, 1 = Masked INT_IIC [27]...
Page 367 SC32442B RISC MICROPROCESSOR INTERRUPT CONTROLLER PRIORITY REGISTER (PRIORITY) Register Address Description Reset Value PRIORITY 0x4A00000C IRQ priority control register 0x7F PRIORITY Description Initial State ARB_SEL6 [20:19] Arbiter 6 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 ARB_SEL5...
Page 368 INTERRUPT CONTROLLER SC32442B RISC MICROPROCESSOR INTERRUPT PENDING (INTPND) REGISTER Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request, which is unmasked and waits for the interrupt to be serviced, has the highest priority . Since the INTPND register is located after the priority logic, only one bit can be set to 1, and that interrupt request generates IRQ to CPU.
Page 369 SC32442B RISC MICROPROCESSOR INTERRUPT CONTROLLER INTPND Description Initial State INT_ADC [31] 0 = Not requested, 1 = Requested INT_RTC [30] 0 = Not requested, 1 = Requested INT_SPI1 [29] 0 = Not requested, 1 = Requested INT_UART0 [28] 0 = Not requested, 1 = Requested INT_IIC [27]...
Page 370 INTERRUPT CONTROLLER SC32442B RISC MICROPROCESSOR INTERRUPT OFFSET (INTOFFSET) REGISTER The value in the interrupt offset register shows which interrupt request of IRQ mode is in the INTPND register. This bit can be cleared automatically by clearing SRCPND and INTPND. Register Address Description Reset Value...
Page 371 SC32442B RISC MICROPROCESSOR INTERRUPT CONTROLLER SUB SOURCE PENDING (SUBSRCPND) REGISTER You can clear a specific bit of the SUBSRCPND register by writing a data to this register. It clears only the bit positions of the SUBSRCPND register corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are.
Page 372 INTERRUPT CONTROLLER SC32442B RISC MICROPROCESSOR INTERRUPT SUB MASK (INTSUBMSK) REGISTER This register has 11 bits each of which is related to an interrupt source. If a specific bit is set to 1, the interrupt request from the corresponding interrupt source is not serviced by the CPU (note that even in such a case, the corresponding bit of the SUBSRCPND register is set to 1).
Page 373: Lcd Controller
SC32442B RISC MICROPROCESSOR LCD CONTROLLER LCD CONTROLLER OVERVIEW The LCD controller in the SC32442B consists of the logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver. The LCD controller supports monochrome, 2-bit per pixel (4-level gray scale) or 4-bit per pixel (16-level gray scale) mode on a monochrome LCD, using a time-based dithering algorithm and Frame Rate Control (FRC) method and it can be interfaced with a color LCD panel at 8-bit per pixel (256-level color) and 12-bit per pixel (4096-level color) for interfacing with STN LCD.
Page 374 — Supports little and big-endian byte ordering, as well as WinCE data formats — Supports 2-type SEC TFT LCD panel (SAMSUNG 3.5” Portrait / 256K Color /Reflective and Transflective a-Si TFT LCD) LTS350Q1-PD1: TFT LCD panel with touch panel and front light unit (Reflective type)
Page 375 SC32442B RISC MICROPROCESSOR LCD CONTROLLER BLOCK DIAGRAM System Bus VCLK /LCD_HCLK TIMEGEN VLINE / HSYNC / CPV REGBANK VFRAME / VSYNC / STV VM / VDEN / TP VIDEO LPC3600 LCD_LPCOE / LCD_LCCINV LCD_LPCREV / LCD_LCCREV LCC3600 LCD_LPCREVB / LCD_LCCREVB LCDCDMA VIDPRCS VD[23:0]...
Page 376 LCD CONTROLLER SC32442B RISC MICROPROCESSOR STN LCD CONTROLLER OPERATION TIMING GENERATOR (TIMEGEN) The TIMEGEN generates the control signals for the LCD driver, such as VFRAME, VLINE, VCLK, and VM. These control signals are closely related to the configuration on the LCDCON1/2/3/4/5 registers in the REGBANK. Based on these programmable configurations on the LCD control registers in the REGBANK, the TIMEGEN can generate the programmable control signals suitable to support many different types of LCD drivers.
Page 377 SC32442B RISC MICROPROCESSOR LCD CONTROLLER Table 15-1. Relation between VCLK and CLKVAL (STN, HCLK=60MHz) CLKVAL 60MHz/X VCLK 60 MHz/4 15.0 MHz 60 MHz/6 10.0 MHz 1023 60 MHz/2046 29.3 kHz VIDEO OPERATION The SC32442B LCD controller supports 8-bit color mode (256 color mode), 12-bit color mode (4096 color mode), 4 level gray scale mode, 16 level gray scale mode as well as the monochrome mode.
Page 378 LCD CONTROLLER SC32442B RISC MICROPROCESSOR 256 Level Color Mode Operation The SC32442B LCD controller can support an 8-bit per pixel 256 color display mode. The color display mode can generate 256 levels of color using the dithering algorithm and FRC. The 8-bit per pixel are encoded into 3-bits for red, 3-bits for green, and 2-bits for blue.
Page 379 SC32442B RISC MICROPROCESSOR LCD CONTROLLER DITHERING AND FRAME RATE CONTROL In case of STN LCD display (except monochrome), video data must be processed by a dithering algorithm. The DITHFRC block has two functions, such as Time-based Dithering Algorithm for reducing flicker and Frame Rate Control (FRC) for displaying gray and color level on the STN panel.
Page 380 LCD CONTROLLER SC32442B RISC MICROPROCESSOR Display Types The LCD controller supports 3 types of LCD drivers: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display mode. Figure 15-2 shows these 3 different display types for monochrome displays, and Figure 15-3 show these 3 different display types for color displays.
Page 381 SC32442B RISC MICROPROCESSOR LCD CONTROLLER MEMORY DATA FORMAT (STN, BSWP=0) Mono 4-bit Dual Scan Display: Video Buffer Memory: LCD Panel A[31] A[30] ..A[0] B[31] B[30] ..B[0] ..Address Data 0000H A[31:0] 0004H B[31:0] • • L[31] L[30] ..L[0] M[31] M[30] ..M[0] ..•...
Page 382 LCD CONTROLLER SC32442B RISC MICROPROCESSOR MEMORY DATA FORMAT ( STN, BSWP=0 ) (CONTINUED) In 4-level gray mode, 2 bits of video data correspond to 1 pixel. In 16-level gray mode, 4 bits of video data correspond to 1 pixel. In 256 level color mode, 8 bits (3 bits of red, 3 bits of green, and 2 bits of blue) of video data correspond to 1 pixel.
Page 383 SC32442B RISC MICROPROCESSOR LCD CONTROLLER 16 BPP Color mode 16 bits (5 bits of red, 6 bits of green, 5 bits of blue) of video data correspond to 1 pixel. But, stn controller will use only 12 bit color data. It means that only upper 4bit each color data will be used as pixel data ( R[15:12], G[10:7], B[4:1]).
Page 384 LCD CONTROLLER SC32442B RISC MICROPROCESSOR 4-bit Dual Scan Display 4-bit Single Scan Display 8-bit Single Scan Display Figure 15-2. Monochrome Display Types (STN) 15-12...
Page 385 SC32442B RISC MICROPROCESSOR LCD CONTROLLER 1 Pixel 4-bit Dual Scan Display 1 Pixel 4-bit Single Scan Display 1 Pixel 8-bit Single Scan Display Figure 15-3. Color Display Types (STN) 15-13...
Page 386 LCD CONTROLLER SC32442B RISC MICROPROCESSOR Timing Requirements Image data should be transferred from the memory to the LCD driver using the VD[7:0] signal. VCLK signal is used to clock the data into the LCD driver's shift register. After each horizontal line of data has been shifted into the LCD driver's shift register, the VLINE signal is asserted to display the line on the panel.
Page 387 SC32442B RISC MICROPROCESSOR LCD CONTROLLER Full Frame Timing(MMODE = 0) INT_FrSyn VFRAME VLINE LINE1LINE2LINE3LINE4LINE5LINE6 LINEn LINE1 Full Frame Timing(MMODE = 1, MVAL=0x2) INT_FrSyn VFRAME VLINE LINE1LINE2LINE3LINE4LINE5LINE6 LINEn LINE1 INT_FrSyn First Line Timing VFRAME LINECNT decreases & Display the 1st line VLINE Display the last line of the previous frame LINECNT...
Page 388 LCD CONTROLLER SC32442B RISC MICROPROCESSOR TFT LCD CONTROLLER OPERATION The TIMEGEN generates the control signals for LCD driver, such as VSYNC, HSYNC, VCLK, VDEN, and LEND signal. These control signals are highly related with the configurations on the LCDCON1/2/3/4/5 registers in the REGBANK.
Page 389 SC32442B RISC MICROPROCESSOR LCD CONTROLLER MEMORY DATA FORMAT (TFT) This section includes some examples of each display mode. 24BPP Display (BSWP = 0, HWSWP = 0, BPP24BL = 0) D[31:24] D[23:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit (BSWP = 0, HWSWP = 0, BPP24BL = 1) D[31:8] D[7:0]...
Page 390 LCD CONTROLLER SC32442B RISC MICROPROCESSOR 16BPP Display (BSWP = 0, HWSWP = 0) D[31:16] D[15:0] 000H 004H 008H (BSWP = 0, HWSWP = 1) D[31:16] D[15:0] 000H 004H 008H ..LCD Panel VD Pin Descriptions at 16BPP (5:6:5) GREEN BLUE (5:5:5:I) GREEN BLUE...
Page 391 SC32442B RISC MICROPROCESSOR LCD CONTROLLER The unused VD pins can be used as GPIO 8BPP Display (BSWP = 0, HWSWP = 0) D[31:24] D[23:16] D[15:8] D[7:0] 000H 004H 008H (BSWP = 1, HWSWP = 0) D[31:24] D[23:16] D[15:8] D[7:0] 000H 004H 008H ..
Page 392 LCD CONTROLLER SC32442B RISC MICROPROCESSOR 4BPP Display (BSWP = 0, HWSWP = 0) D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H 004H 008H (BSWP = 1, HWSWP = 0) D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H 004H 008H 2BPP Display (BSWP = 0, HWSWP = 0)
Page 393 SC32442B RISC MICROPROCESSOR LCD CONTROLLER 256 PALETTE USAGE (TFT) Palette Configuration and Format Control The SC32442B provides 256 color palette for TFT LCD Control. The user can select 256 colors from the 64K colors in these two formats. The 256 color palette consists of the 256 (depth) x 16-bit SPSRAM. The palette supports 5:6:5 (R:G:B) format and 5:5:5:1(R:G:B:I) format.
Page 394 LCD CONTROLLER SC32442B RISC MICROPROCESSOR A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] LCD Panel 16BPP 5:5:5+1 Format(Non-Palette) A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] A[15] A[14] A[13] A[12]A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] LCD Panel...
Page 395 SC32442B RISC MICROPROCESSOR LCD CONTROLLER INT_FrSyn VSYNC HSYNC VDEN VBPD+1 VFPD+1 LINEVAL +1 VSPW+1 1 Frame 1 Line HSYNC VCLK VDEN LEND HBPD+1 HFPD+1 HOZVAL+1 HSPW+1 Figure 15-6. TFT LCD Timing Example 15-23...
Page 396 LCD CONTROLLER SC32442B RISC MICROPROCESSOR SAMSUNG TFT LCD PANEL (3.5” PORTRAIT / 256K COLOR / REFLECTIVE A-SI/TRANSFLECTIVE A-SI TFT LCD) The SC32442B supports following SEC TFT LCD panels. 1. SAMSUNG 3.5” Portrait / 256K Color /Reflective a-Si TFT LCD. LTS350Q1-PD1: TFT LCD panel with touch panel and front light unit LTS350Q1-PD2: TFT LCD panel only 2.
Page 397 SC32442B RISC MICROPROCESSOR LCD CONTROLLER VIRTUAL DISPLAY (TFT/STN) The SC32442B supports hardware horizontal or vertical scrolling. If the screen is scrolled, the fields of LCDBASEU and LCDBASEL in LCDSADDR1/2 registers need to be changed (see Figure 15-8), except the values of PAGEWIDTH and OFFSIZE. The video buffer in which the image is stored should be larger than the LCD panel screen in size.
Page 398 LCD CONTROLLER SC32442B RISC MICROPROCESSOR LCD POWER ENABLE (STN/TFT) The SC32442B provides Power enable (PWREN) function. When PWREN is set to make PWREN signal enabled, the output value of LCD_PWREN pin is controlled by ENVID. In other words, If LCD_PWREN pin is connected to the power on/off control pin of the LCD panel, the power of LCD panel is controlled by the setting of ENVID automatically.
Page 399 SC32442B RISC MICROPROCESSOR LCD CONTROLLER LCD CONTROLLER SPECIAL REGISTERS LCD Control 1 Register Register Address Description Reset Value LCDCON1 0X4D000000 LCD control 1 register 0x00000000 LCDCON1 Description Initial State LINECNT [27:18] Provide the status of the line counter. 0000000000 (read only) Down count from LINEVAL to 0 CLKVAL [17:8]...
Page 400 LCD CONTROLLER SC32442B RISC MICROPROCESSOR LCD Control 2 Register Register Address Description Reset Value LCDCON2 0X4D000004 LCD control 2 register 0x00000000 LCDCON2 Description Initial State TFT: Vertical back porch is the number of inactive lines at the start VBPD [31:24] 0x00 of a frame, after vertical synchronization period.
Page 401 SC32442B RISC MICROPROCESSOR LCD CONTROLLER LCD Control 3 Register Register Address Description Reset Value LCDCON3 0X4D000008 LCD control 3 register 0x00000000 LCDCON3 Description Initial state TFT: Horizontal back porch is the number of VCLK periods between HBPD (TFT) [25:19] 0000000 the falling edge of HSYNC and the start of active data.
Page 402 LCD CONTROLLER SC32442B RISC MICROPROCESSOR LCD Control 4 Register Register Address Description Reset Value LCDCON4 0X4D00000C LCD control 4 register 0x00000000 LCDCON4 Description Initial state STN: These bit define the rate at which the VM signal will toggle if MVAL [15:8] 0X00 the MMODE bit is set to logic '1'.
Page 403 SC32442B RISC MICROPROCESSOR LCD CONTROLLER LCD Control 5 Register Register Address Description Reset Value LCDCON5 0X4D000010 LCD control 5 register 0x00000000 LCDCON5 Description Initial state Reserved [31:17] This bit is reserved and the value should be ‘0’. TFT: Vertical Status (read only). VSTATUS [16:15] 00 = VSYNC...
Page 404 LCD CONTROLLER SC32442B RISC MICROPROCESSOR LCD Control 5 Register (Continued) LCDCON5 Description Initial state TFT: This bit indicates the VDEN signal polarity. INVVDEN 0 = normal 1 = inverted STN/TFT: This bit indicates the PWREN signal polarity. INVPWREN 0 = normal 1 = inverted TFT: This bit indicates the LEND signal polarity.
Page 405 SC32442B RISC MICROPROCESSOR LCD CONTROLLER FRAME BUFFER START ADDRESS 1 REGISTER Register Address Description Reset Value STN/TFT: Frame buffer start address 1 register LCDSADDR1 0X4D000014 0x00000000 LCDSADDR1 Description Initial State LCDBANK [29:21] These bits indicate A[30:22] of the bank location for the video buffer 0x00 in the system memory.
Page 406 LCD CONTROLLER SC32442B RISC MICROPROCESSOR FRAME Buffer Start Address 3 Register Register Address Description Reset Value STN/TFT: Virtual screen address set LCDSADDR3 0X4D00001C 0x00000000 LCDSADDR3 Description Initial State OFFSIZE [21:11] Virtual screen offset size (the number of half words). 00000000000 This value defines the difference between the address of the last half word displayed on the previous LCD line and the address of the first half word to be displayed in the new LCD line.
Page 407 SC32442B RISC MICROPROCESSOR LCD CONTROLLER RED Lookup Table Register Register Address Description Reset Value STN: Red lookup table register REDLUT 0X4D000020 0x00000000 REDLUT Description Initial State REDVAL [31:0] These bits define which of the 16 shades will be chosen by each of 0x00000000 the 8 possible red combinations.
Page 408 LCD CONTROLLER SC32442B RISC MICROPROCESSOR Dithering Mode Register Register Address Description Reset Value STN: Dithering mode register. DITHMODE 0X4D00004C 0x00000 This register reset value is 0x00000 But, user can change this value to 0x12210. (Refer to a sample program source for the latest value of this register.) DITHMODE Description...
Page 409 SC32442B RISC MICROPROCESSOR LCD CONTROLLER Temp Palette Register Register Address Description Reset Value TFT: Temporary palette register. TPAL 0X4D000050 0x00000000 This register value will be video data at next frame. TPAL Description Initial state TPALEN [24] Temporary palette register enable bit. 0 = Disable 1 = Enable TPALVAL...
Page 410 LCD CONTROLLER SC32442B RISC MICROPROCESSOR LCD Interrupt Pending Register Register Address Description Reset Value LCDINTPND 0X4D000054 Indicate the LCD interrupt pending register LCDINTPND Description Initial state INT_FrSyn LCD frame synchronized interrupt pending bit. 0 = The interrupt has not been requested. 1 = The frame has asserted the interrupt request.
Page 411 SC32442B RISC MICROPROCESSOR LCD CONTROLLER LCD Interrupt Mask Register Register Address Description Reset Value LCDINTMSK 0X4D00005C Determine which interrupt source is masked. The masked interrupt source will not be serviced. LCDINTMSK Description Initial state FIWSEL Determine the trigger level of LCD FIFO. 0 = 4 words 1 = 8 words INT_FrSyn...
Page 412 LCD CONTROLLER SC32442B RISC MICROPROCESSOR TCON Control Register Register Address Description Reset Value TCONSEL 0X4D000060 This register controls the LPC3600/LCC3600 0xF84 modes. TCONSEL Description Initial state LCC_TEST2 [11] LCC3600 Test Mode 2 ( Read Only ) LCC_TEST1 [10] LCC3600 Test Mode 1 ( Read Only ) LCC_SEL5 Select STV polarity LCC_SEL4...
Page 413 SC32442B RISC MICROPROCESSOR LCD CONTROLLER Register Setting Guide (STN) The LCD controller supports multiple screen sizes by special register setting. The CLKVAL value determines the frequency of VCLK. This value has to be determined such that the VCLK value is greater than data transmission rate. The data transmission rate for the VD port of the LCD controller is used to determine the value of CLKVAL register.
Page 414 LCD CONTROLLER SC32442B RISC MICROPROCESSOR Example 1: 160 x 160, 4-level gray, 80 frame/sec, 4-bit single scan display, HCLK frequency is 60 MHz WLH = 1, WDLY = 1. Data transmission rate = 160 x 160 x 80 x 1/4 = 512 kHz CLKVAL = 58, VCLK = 517KHz HOZVAL = 39,...
Page 415 LCD. Select the gray level quality through the following procedures: 1. Get the latest dithering pattern register value from SAMSUNG. 2. Display 16 gray bar in LCD. 3. Change the frame rate into an optimal value.
Page 416 LCD CONTROLLER SC32442B RISC MICROPROCESSOR Register Setting Guide (TFT LCD) The CLKVAL register value determines the frequency of VCLK and frame rate. Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } x {(HSPW+1) + (HBPD +1) + (HFPD+1) + (HOZVAL + 1) } x { 2 x ( CLKVAL+1 ) / ( HCLK ) } ] For applications, the system timing must be considered to avoid under-run condition of the fifo of the lcd controller caused by memory bandwidth contention.
Page 417 SC32442B RISC MICROPROCESSOR LCD CONTROLLER NOTES 15-45...
Page 418 SC32442B RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC & TOUCH SCREEN INTERFACE OVERVIEW The 10-bit CMOS ADC (Analog to Digital Converter) is a recycling type device with 8-channel analog inputs. It converts the analog input signal into 10-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.5MHz A/D converter clock.
Page 419 ADC AND TOUCH SCREEN INTERFACE SC32442B RISC MICROPROCESSOR ADC & TOUCH SCREEN INTERFACE OPERATION BLOCK DIAGRAM Figure 16-1 shows the functional block diagram of A/D converter and Touch Screen Interface. Note that the A/D converter device is a recycling type. AVDD Touch Screen Pads control...
Page 420 SC32442B RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE FUNCTION DESCRIPTIONS A/D Conversion Time When the GCLK frequency is 50MHz and the prescaler value is 49, total 10-bit conversion time is as follows. A/D converter freq. = 50MHz/(49+1) = 1MHz Conversion time = 1/(1MHz / 5cycles) = 1/200KHz = 5 us NOTE This A/D converter was designed to operate at maximum 2.5MHz clock, so the conversion rate can go up to 500 KSPS.
Page 421 ADC AND TOUCH SCREEN INTERFACE SC32442B RISC MICROPROCESSOR Programming Notes The A/D converted data can be accessed by means of interrupt or polling method. With interrupt method the overall conversion time - from A/D converter start to converted data read - may be delayed because of the return time of interrupt service routine and data access time.
Page 422 SC32442B RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS ADC CONTROL REGISTER (ADCCON) Register Address Description Reset Value ADCCON 0x5800000 ADC Control Register 0x3FC4 ADCCON Description Initial State ECFLG [15] End of conversion flag(Read only) 0 = A/D conversion in process 1 = End of A/D conversion PRSCEN...
Page 423 ADC AND TOUCH SCREEN INTERFACE SC32442B RISC MICROPROCESSOR ADC TOUCH SCREEN CONTROL REGISTER (ADCTSC) Register Address Description Reset Value ADCTSC 0x5800004 ADC Touch Screen Control Register 0x58 ADCTSC Description Initial State UD_SEN Detect Stylus Up or Down status. 0 = Detect Stylus Down Interrupt Signal. 1 = Detect Stylus Up Interrupt Signal.
Page 424 SC32442B RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC START DELAY REGISTER (ADCDLY) Register Address Description Reset Value ADCDLY 0x5800008 ADC Start or Interval Delay Register 0x00ff ADCDLY Description Initial State DELAY [15:0] 1) Normal Conversion Mode, XY Position Mode, Auto Position Mode. 00ff →...
Page 425 ADC AND TOUCH SCREEN INTERFACE SC32442B RISC MICROPROCESSOR ADC CONVERSION DATA REGISTER (ADCDAT0) Register Address Description Reset Value ADCDAT0 0x580000C ADC Conversion Data Register ADCDAT0 Description Initial State UPDOWN [15] Up or Down state of Stylus at Waiting for Interrupt Mode. 0 = Stylus down state.
Page 426 SC32442B RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC CONVERSION DATA REGISTER (ADCDAT1) Register Address Description Reset Value ADCDAT1 0x5800010 ADC Conversion Data Register ADCDAT1 Description Initial State UPDOWN [15] Up or Down state of Stylus at Waiting for Interrupt Mode. 0 = Stylus down state.
Page 427 ADC AND TOUCH SCREEN INTERFACE SC32442B RISC MICROPROCESSOR NOTES 16-10...
Page 428: Real Time Clock
SC32442B RISC MICROPROCESSOR REAL TIME CLOCK REAL TIME CLOCK OVERVIEW The Real Time Clock (RTC) unit can be operated by the backup battery while the system power is off. The RTC can transmit 8-bit data to CPU as Binary Coded Decimal (BCD) values using the STRB/LDRB ARM operation. The data include the time by second, minute, hour, date, day, month, and year.
Page 429 REAL TIME CLOCK SC32442B RISC MICROPROCESSOR REAL TIME CLOCK OPERATION TICNT TIME TICK Time Tick Generator 128 Hz,or TICNT2CLK RTCRST Clock Divider Reset Register Leap Year Generator XTIrtc 1 Hz HOUR DATE YEAR XTOrtc Control Register Alarm Generator RTCCON RTCALM PMWKU INT_RTC Figure 17-1.
Page 430 SC32442B RISC MICROPROCESSOR REAL TIME CLOCK ALARM FUNCTION The RTC generates an alarm signal at a specified time in the power-off mode or normal operation mode. In normal operation mode, the alarm interrupt (INT_RTC) is activated. In the power-off mode, the power management wakeup (PMWKUP) signal is activated as well as the INT_RTC.
Page 431 REAL TIME CLOCK SC32442B RISC MICROPROCESSOR REAL TIME CLOCK SPECIAL REGISTERS REAL TIME CLOCK CONTROL (RTCCON) REGISTER The RTCCON register consists of 4 bits such as the RTCEN, which controls the read/write enable of the BCD registers, CLKSEL, CNTSEL, and CLKRST for testing. RTCEN bit can control all interfaces between the CPU and the RTC, so it should be set to 1 in an RTC control routine to enable data read/write after a system reset.
Page 432 SC32442B RISC MICROPROCESSOR REAL TIME CLOCK RTC ALARM CONTROL (RTCALM) REGISTER The RTCALM register determines the alarm enable and the alarm time. Please note that the RTCALM register generates the alarm signal through both INT_RTC and PMWKUP in power down mode, but only through INT_RTC in the normal operation mode.
Page 433 REAL TIME CLOCK SC32442B RISC MICROPROCESSOR ALARM SECOND DATA (ALMSEC) REGISTER Register Address Description Reset Value ALMSEC 0x57000054(L) Alarm second data register 0x57000057(B) (by byte) ALMSEC Description Initial State Reserved SECDATA [6:4] BCD value for alarm second. 0 ~ 5 [3:0] 0 ~ 9 0000...
Page 434 SC32442B RISC MICROPROCESSOR REAL TIME CLOCK ALARM DATE DATA (ALMDATE) REGISTER Register Address Description Reset Value ALMDATE 0x57000060(L) Alarm date data register 0x01 0x57000063(B) (by byte) ALMDATE Description Initial State Reserved [7:6] DATEDATA [5:4] BCD value for alarm date, from 0 to 28, 29, 30, 31. 0 ~ 3 [3:0] 0 ~ 9...
Page 435 REAL TIME CLOCK SC32442B RISC MICROPROCESSOR BCD SECOND (BCDSEC) REGISTER Register Address Description Reset Value BCDSEC 0x57000070(L) BCD second register Undefined 0x57000073(B) (by byte) BCDSEC Description Initial State SECDATA [6:4] BCD value for second. 0 ~ 5 [3:0] 0 ~ 9 BCD MINUTE (BCDMIN) REGISTER Register Address...
Page 436 SC32442B RISC MICROPROCESSOR REAL TIME CLOCK BCD DATE (BCDDATE) REGISTER Register Address Description Reset Value BCDDATE 0x5700007C(L) BCD date register Undefined 0x5700007F(B) (by byte) BCDDATE Description Initial State Reserved [7:6] DATEDATA [5:4] BCD value for date. 0 ~ 3 [3:0] 0 ~ 9 BCD DAY (BCDDAY) REGISTER Register...
Page 437 REAL TIME CLOCK SC32442B RISC MICROPROCESSOR BCD YEAR (BCDYEAR) REGISTER Register Address Description Reset Value BCDYEAR 0x57000088(L) BCD year register Undefined 0x5700008B(B) (by byte) BCDYEAR Description Initial State YEARDATA [7:0] BCD value for year. 00 ~ 99 RTC LOWBAT CHECK (RTCLBAT) REGISTER Register Address Description...
Page 438 SC32442B RISC MICROPROCESSOR REAL TIME CLOCK RTC TICK TIME COUNTER 2 (TICCNT2) REGISTER Register Address Description Reset Value TICCNT2 0x57000090(L) Tick time count 2 register Undefined TICCNT2 Description Initial State TICCNT 2 [15:0] 16 bit tick time count 2 value 16’b0 RTC TICK TIME COUNTER 2 CONTROL REGISTER Register...
Page 439 REAL TIME CLOCK SC32442B RISC MICROPROCESSOR TICK TIME CURRENT COUNTER READ REGISTER Register Address Description Reset Value TICCURCNT 0x57000098(L) Current tick count value Undefined CURTICCNT Description Initial State TICCURCNT [15:0] Current tick count value Note) if TICCNT[7] and TICCNT2CON[3] & disabled, TICCURCNT should be “0”. If you want to read the current tick counter value, read the TICCURCNT value and then disable the TICCNT[7] and TICCNT2CON[3] RTC TICK TIME COUNTER SELECTION REGISTER Register...
Page 440: Watchdog Timer
SC32442B RISC MICROPROCESSOR WATCHDOG TIMER WATCHDOG TIMER OVERVIEW The SC32442B watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors. It can be used as a normal 16-bit interval timer to request interrupt service.
Page 441 WATCHDOG TIMER SC32442B RISC MICROPROCESSOR WATCHDOG TIMER OPERATION Figure 18-1 shows the functional block diagram of the watchdog timer. The watchdog timer uses only PCLK as its source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer clock, and the resulting frequency is divided again.
Page 442 SC32442B RISC MICROPROCESSOR WATCHDOG TIMER WATCHDOG TIMER SPECIAL REGISTERS WATCHDOG TIMER CONTROL (WTCON) REGISTER The WTCON register allows the user to enable/disable the watchdog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watchdog timer output.The Watchdog timer is used to resume the SC32442B restart on mal-function after its power on;...
Page 443 WATCHDOG TIMER SC32442B RISC MICROPROCESSOR WATCHDOG TIMER DATA (WTDAT) REGISTER The WTDAT register is used to specify the time-out duration. The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation. However, using 0x8000 (initial value) will drive the first time-out.
Page 444 SC32442B RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER MMC/SD/SDIO Controller FEATURES SD Memory Card Spec(ver 1.0) / MMC Spec(2.11) compatible SDIO Card Spec(Ver 1.0) compatible 16 words(64 bytes) FIFO for data Tx/Rx 40-bit Command Register 136-bit Response Register 8-bit Prescaler logic(Freq = System Clock / (P + 1)) Normal, and DMA data transfer mode(byte, halfword, word transfer) DMA burst4 access support(only word transfer) 1bit / 4bit(wide bus) mode &...
Page 445 MMC/SD/SDIO CONTROLLER SC32442B RISC MICROPROCESSOR SD OPERATION A serial clock line synchronizes shifting and sampling of the information on the five data lines. The transmission frequency is controlled by making the appropriate bit settings to the SDIPRE register. You can modify its frequency to adjust the baud rate data register value.
Page 446 SC32442B RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER SDIO OPERATION There are two functions of SDIO operation: SDIO Interrupt receiving and Read Wait Request generation. These two functions can operate when RcvIOInt bit and RwaitEn bit of SDICON register is activated respectively. And two functions have the steps and conditions like below.
Page 447 MMC/SD/SDIO CONTROLLER SC32442B RISC MICROPROCESSOR SDI SPECIAL REGISTERS SDI Control Register(SDICON) Register Address Description Reset Value SDICON 0x5A000000 SDI Control Register SDICON Description Initial Value Reserved [31:9] SDMMC Reset Reset whole sdmmc block. This bit is automatically cleared. (SDreset) 0 = normal mode, 1 = SDMMC reset Reserved [7:6]...
Page 448 SC32442B RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER SDI Command Argument Register(SDICmdArg) Register Address Description Reset Value SDICmdArg 0x5A000008 SDI Command Argument Register SDICmdArg Description Initial Value CmdArg [31:0] Command Argument 0x00000000 SDI Command Control Register(SDICmdCon) Register Address Description Reset Value SDICmdCon 0x5A00000C SDI Command Control Register SDICommand Description...
Page 449 MMC/SD/SDIO CONTROLLER SC32442B RISC MICROPROCESSOR SDI Command Status Register(SDICmdSta) Register Address Description Reset Value SDICmdSta 0x5A000010 R/(C) SDI Command Status Register SDICmdSta Description Initial Value Reserved [31:13] Response CRC [12] CRC check failed when command response received. This flag is Fail(RspCrc) cleared by setting to one this bit.
Page 450 SC32442B RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER SDI Response Register 2(SDIRSP2) Register Address Description Reset Value SDIRSP2 0x5A00001C SDI Response Register 2 SDIRSP2 Description Initial Value Response2 [31:0] unused(short), card status[63:32](long) 0x00000000 SDI Response Register 3(SDIRSP3) Register Address Description Reset Value SDIRSP3 0x5A000020 SDI Response Register 3 SDIRSP3...
Page 451 MMC/SD/SDIO CONTROLLER SC32442B RISC MICROPROCESSOR SDI Data Control Register(SDIDatCon) Register Address Description Reset Value SDIDatCon 0x5A00002C SDI Data control Register SDIDatCon Description Initial Value Reserved [31:25] Burst4 enable [24] Enable Burst4 mode in DMA mode. This bit should be set only (Burst4) when Data Size is word.
Page 452 SC32442B RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER SDI Data Remain Counter Register(SDIDatCnt) Register Address Description Reset Value SDIDatCnt 0x5A000030 SDI Data Remain Counter Register SDIDatCnt Description Initial Value Reserved [31:24] BlkNumCnt [23:12] Remaining Block number 0x000 BlkCnt [11:0] Remaining data byte of 1 block 0x000 SDI Data Status Register(SDIDatSta) Register...
Page 453 MMC/SD/SDIO CONTROLLER SC32442B RISC MICROPROCESSOR SDI FIFO Status Register(SDIFSTA) Register Address Description Reset Value SDIFSTA 0x5A000038 R/(C) SDI FIFO Status Register SDIFSTA Description Initial State Reserved [31:16] FIFO Reset(FRST) [16] Reset FIFO value. This bit is automatically cleared. 0 = normal mode, 1 = FIFO reset FIFO Fail error [15:14]...
Page 454 SC32442B RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER SDI Interrupt Mask Register(SDIIntMsk) Register Address Description Reset Value SDIIntMsk 0x5A00003C SDI Interrupt Mask Register SDIIntMsk Description Initial Value Reserved [31:19] NoBusy Interrupt [18] Determines SDI generate an interrupt if busy signal is not active Enable (NoBusyInt) 0 = disable, 1 = interrupt enable...
Page 455 MMC/SD/SDIO CONTROLLER SC32442B RISC MICROPROCESSOR Enable (RFHalfInt) 0 = disable, 1 = interrupt enable SDI Data Register(SDIDAT) Register Address Description Reset Value SDIDAT 0x5A000040, 44, 48, 4C(Li/W, SDI Data Register Li/HW, Li/B, Bi/W) 0x5A000041(Bi/HW), 0x5A000043(Bi/B) SDIDAT Description Initial State Data Register [31:0] This field contains the data to be transmitted or received over the 0x00000000...
Page 456 SC32442B RISC MICROPROCESSOR IIC-BUS INTERFACE IIC-BUS INTERFACE OVERVIEW The SC32442B RISC microprocessor can support a multi-master IIC-bus serial interface. A dedicated serial data line (SDA) and a serial clock line (SCL) carry information between bus masters and peripheral devices which are connected to the IIC-bus.
Page 457 IIC-BUS INTERFACE SC32442B RISC MICROPROCESSOR Address Register Comparator IIC-Bus Control Logic IICCON IICSTAT 4-bit Prescaler Shift Register PCLK Shift Register (IICDS) Data Bus Figure 20-1. IIC-Bus Block Diagram 20-2...
Page 458 SC32442B RISC MICROPROCESSOR IIC-BUS INTERFACE IIC-BUS INTERFACE The SC32442B IIC-bus interface has four operation modes: — Master transmitter mode — Master receive mode — Slave transmitter mode — Slave receive mode Functional relationships among these operating modes are described below. START AND STOP CONDITIONS When the IIC-bus interface is inactive, it is usually in Slave mode.
Page 459 IIC-BUS INTERFACE SC32442B RISC MICROPROCESSOR DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. The bytes can be unlimitedly transmitted per transfer. The first byte following a Start condition should have the address field. The address field can be transmitted by the master when the IIC-bus is operating in Master mode.
Page 460 SC32442B RISC MICROPROCESSOR IIC-BUS INTERFACE The receiver should also drive the SDA line Low during the ACK clock pulse so that the SDA keeps Low during the High period of the ninth SCL pulse. The ACK bit transmit function can be enabled or disabled by software (IICSTAT). However, the ACK pulse on the ninth clock of SCL is required to complete the one-byte data transfer operation.
Page 461 IIC-BUS INTERFACE SC32442B RISC MICROPROCESSOR READ-WRITE OPERATION In Transmitter mode, when the data is transferred, the IIC-bus interface will wait until IIC-bus Data Shift (IICDS) register receives a new data. Before the new data is written into the register, the SCL line will be held low, and then released after it is written.
Page 462 SC32442B RISC MICROPROCESSOR IIC-BUS INTERFACE FLOWCHARTS OF OPERATIONS IN EACH MODE The following steps must be executed before any IIC Tx/Rx operations. 1) Write own slave address on IICADD register, if needed. 2) Set IICCON register. a) Enable interrupt b) Define SCL period 3) Set IICSTAT to enable Serial Output START Master Tx mode has...
Page 463 IIC-BUS INTERFACE SC32442B RISC MICROPROCESSOR START Master Rx mode has been configured. Write slave address to IICDS. Write 0xB0 (M/R Start) to IICSTAT. The data of the IICDS (slave address) is transmitted. ACK period and then interrupt is pending. Stop? Read a new data from Write 0x90 (M/R Stop) IICDS.
Page 464 SC32442B RISC MICROPROCESSOR IIC-BUS INTERFACE START Slave Tx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Matched? The IIC address match interrupt is generated. Write data to IICDS. Clear pending bit to resume.
Page 465 IIC-BUS INTERFACE SC32442B RISC MICROPROCESSOR START Slave Rx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Matched? The IIC address match interrupt is generated. Read data from IICDS. Clear pending bit to resume.
Page 466 SC32442B RISC MICROPROCESSOR IIC-BUS INTERFACE IIC-BUS INTERFACE SPECIAL REGISTERS MULTI-MASTER IIC-BUS CONTROL (IICCON) REGISTER Register Address Description Reset Value IICCON 0x54000000 IIC-Bus control register 0x0X IICCON Description Initial State IIC-bus acknowledge enable bit. Acknowledge generation 0 : Disable 1 : Enable In Tx mode, the IICSDA is free in the ack time.
Page 467 IIC-BUS INTERFACE SC32442B RISC MICROPROCESSOR MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTER Register Address Description Reset Value IICSTAT 0x54000004 IIC-Bus control/status register IICSTAT Description Initial State Mode selection [7:6] IIC-bus master/slave Tx/Rx mode select bits. 00 : Slave receive mode 01 : Slave transmit mode 10 : Master receive mode 11 : Master transmit mode Busy signal status /...
Page 468 SC32442B RISC MICROPROCESSOR IIC-BUS INTERFACE MULTI-MASTER IIC-BUS ADDRESS (IICADD) REGISTER Register Address Description Reset Value IICADD 0x54000008 IIC-Bus address register 0xXX IICADD Description Initial State Slave address [7:0] 7-bit slave address, latched from the IIC-bus. XXXXXXXX When serial output enable = 0 in the IICSTAT, IICADD is write-enabled.
Page 469 IIC-BUS INTERFACE SC32442B RISC MICROPROCESSOR MULTI-MASTER IIC-BUS LINE CONTROL(IICLC) REGISTER Register Address Description Reset Value IICLC 0x54000010 IIC-Bus multi-master line control register 0x00 IICLC Description Initial State Filter Enable IIC-bus filter enable bit. When SDA port is operating as input, this bit should be High.
Page 470 SC32442B RISC MICROPROCESSOR IIS-BUS INTERFACE IIS-BUS INTERFACE OVERVIEW Currently, many digital audio systems are attracting the consumers on the market, in the form of compact discs, digital audio tapes, digital sound processors, and digital TV sound. The SC32442B Inter-IC Sound (IIS) bus interface can be used to implement a CODEC interface to an external 8/16-bit stereo audio CODEC IC for mini- disc and portable applications.
Page 471: Functional Descriptions
IIS-BUS INTERFACE SC32442B RISC MICROPROCESSOR BLOCK DIAGRAM TxFIFO ADDR DATA BRFC SFTR CNTL RxFIFO CHNC SCLK IPSR_A PCLK SCLKG LRCK IPSR_B CDCLK MPLLin Figure 21-1. IIS-Bus Block Diagram FUNCTIONAL DESCRIPTIONS Bus interface, register bank, and state machine (BRFC): Bus interface logic and FIFO access are controlled by the state machine.
Page 472 SC32442B RISC MICROPROCESSOR IIS-BUS INTERFACE DMA TRANSFER In this mode, transmit or receive FIFO is accessible by the DMA controller. DMA service request in transmit or receive mode is made by the FIFO ready flag automatically. TRANSMIT AND RECEIVE MODE In this mode, IIS bus interface can transmit and receive data simultaneously.
Page 473 IIS-BUS INTERFACE SC32442B RISC MICROPROCESSOR LRCK LEFT RIGHT LEFT SCLK N-1th N-1th (1st) (last) (1st) (last) (1st) IIS-bus Format (N=8 or 16) LRCK LEFT RIGHT SCLK N-1th N-1th (1st) (last) (1st) (last) MSB-justified Format (N=8 or 16) Figure 21-2. IIS-Bus and MSB (Left)-justified Data Interface Formats SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency (PCLK or MPLLin) can be selected by sampling frequency as shown in Table 21-1.
Page 474 SC32442B RISC MICROPROCESSOR IIS-BUS INTERFACE @CODECLK = 384fs 16fs, 32fs, 48fs 32fs, 48fs IIS-BUS INTERFACE SPECIAL REGISTERS IIS CONTROL (IISCON) REGISTER Register Address Description Reset Value IISCON 0x55000000 (Li/HW, Li/W, Bi/W) IIS control register 0x100 0x55000002 (Bi/HW) IISCON Description Initial State Left/Right channel index 0 = Left (Read only)
Page 475 IIS-BUS INTERFACE SC32442B RISC MICROPROCESSOR IIS MODE REGISTER (IISMOD) REGISTER Register Address Description Reset Value IISMOD 0x55000004 (Li/W, Li/HW, Bi/W) IIS mode register 0x55000006 (Bi/HW) IISMOD Description Initial State Master Clock Select Master clock select 0 = PCLK 1 = MPLLin Master/slave mode select 0 = Master mode (IISLRCK and IISCLK are output mode).
Page 476 SC32442B RISC MICROPROCESSOR IIS-BUS INTERFACE IIS PRESCALER (IISPSR) REGISTER Register Address Description Reset Value IISPSR 0x55000008 (Li/HW, Li/W, Bi/W) IIS prescaler register 0x5500000A (Bi/HW) IISPSR Description Initial State Prescaler control A [9:5] Data value: 0 ~ 31 00000 Note: Prescaler A makes the master clock that is used the internal block and division factor is N+1.
Page 477 IIS-BUS INTERFACE SC32442B RISC MICROPROCESSOR IIS FIFO CONTROL (IISFCON) REGISTER Register Address Description Reset Value IISFCON 0x5500000C (Li/HW, Li/W, Bi/W) IIS FIFO interface register 0x5500000E (Bi/HW) IISFCON Description Initial State Transmit FIFO access mode select [15] 0 = Normal 1 = DMA Receive FIFO access mode select [14] 0 = Normal...
Page 478 SC32442B RISC MICROPROCESSOR OVERVIEW The SC32442B Serial Peripheral Interface (SPI) can interface with the serial data transfer. The SC32442B includes two SPI, each of which has two 8-bit shift registers for transmission and receiving, respectively. During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). 8-bit serial data at a frequency is determined by its corresponding control register settings.
Page 479 SC32442B RISC MICROPROCESSOR BLOCK DIAGRAM SPIMISO 0 MISO Data Tx 8bit Shift Reg 0 Slave Master SPIMOSI 0 Master Rx 8bit Shift Reg 0 MOSI Slave Clock SPI Clock SPICLK 0 8bit Prescaler 0 PCLK CLOCK (Master) Slave Logic 0 Master CPOL Prescaler Register 0...
Page 480 SC32442B RISC MICROPROCESSOR SPI OPERATION Using the SPI interface, SC32442B can send/receive 8-bit data simultaneously with an external device. A serial clock line is synchronized with the two data lines for shifting and sampling of the information. When the SPI is the master, transmission frequency can be controlled by setting the appropriate bit in SPPREn register.
Page 481 SC32442B RISC MICROPROCESSOR SPI TRANSFER FORMAT The SC32442B supports 4 different formats to transfer data. Figure 22-2 shows the four waveforms for SPICLK. CPOL = 0, CPHA = 0 (Format A) Cycle SPICLK MOSI MISO *MSB *MSB : MSB of previous frame CPOL = 0, CPHA = 1 (Format B) Cycle SPICLK...
Page 482 SC32442B RISC MICROPROCESSOR TRANSMITTING PROCEDURE FOR DMA 1. SPI is configured as DMA mode. 2. DMA is configured properly. 3. SPI requests DMA service. 4. DMA transmits 1byte data to the SPI. 5. SPI transmits the data to card. 6. Return to Step 3 until DMA count becomes 0. 7.
Page 483 SC32442B RISC MICROPROCESSOR SPI SPECIAL REGISTERS SPI CONTROL REGISTER Register Address Description Reset Value SPCON0 0x59000000 SPI channel 0 control register 0x00 SPCON1 0x59000020 SPI channel 1 control register 0x00 SPCONn Description Initial State SPI Mode Select [6:5] Determine how SPTDAT is read/written (SMOD) 00 = polling mode 01 = interrupt mode...
Page 484 SC32442B RISC MICROPROCESSOR SPI STATUS REGISTER Register Address Description Reset Value SPSTA0 0x59000004 SPI channel 0 status register 0x01 SPSTA1 0x59000024 SPI channel 1 status register 0x01 SPSTAn Description Initial State Reserved [7:3] Data Collision This flag is set if the SPTDATn is written or SPRDATn is read Error Flag (DCOL) while a transfer is in progress and cleared by reading the SPSTAn.
Page 485 SC32442B RISC MICROPROCESSOR SPI is configured as a master, SPIMISO (MISO) is the master data input line, SPIMOSI (MOSI) is the master data output line, and SPICLK (SCK) is the clock output line. When SPI becomes a slave, these pins perform reverse roles.
Page 486: Camera Interface
SC32442B RISC MICROPROCESSOR CAMERA INTERFACE CAMERA INTERFACE OVERVIEW This chapter will explain the specification and defines the camera interface. CAMIF (CAMera InterFace) within the SC32442B consists of 7 parts – pattern mux, capturing unit, preview scaler, codec scaler, preview DMA, codec DMA, and SFR.
Page 487 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE BLOCK DIAGRAM T_patternMux CatchCam ITU-R BT 601/656 CamI f YCbCr 4:2:2 Preview Scaler & Codec Scaler RGB Formatter Preview DMA Codec DMA AHB bus Figure 23-1 CAMIF Overview 23-2...
Page 488 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE TIMING DIAGRAM 1 frame CAMVSYNC Vertical lines CAMHREF CAMHREF Horizontal width (1H) CAMPCLK 8-bit mode CAMDATA [7:0] Figure 23-2 ITU-R BT 601 Input Timing Diagram CAMPCLK CAMDATA [7:0] Video timing Video timing reference codes reference codes Pixel data Figure 23-3 ITU-R BT 656 Input Timing Diagram There are two timing reference signals in ITU-R BT 656 format, one is at the beginning of each video data block...
Page 489 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE Table 23-2 Video Timing Reference Codes of ITU-656 Format Data bit number First word Second word Third word Fourth word 9 (MSB) 1 (NOTE) For compatibility with existing 8-bit interfaces, the values of bits D1 and D0 are not defined. F = 0 (during field 1), 1 (during field 2) V = 0 (elsewhere), 1 (during field blanking) H = 0 (in SAV: Start of Active Video), 1 (in EAV: End of Active Video)
Page 490 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE CAMERA INTERFACE OPERATION TWO DMA PATHS CAMIF has 2 DMA paths. P-path (Preview path) and C-path (Codec path) are separated from each other on the AHB bus. In view of the system bus, both the paths are independent. The P-path stores the RGB image data into memory for PIP.
Page 491 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE mal-functioning Variable USB PLL UPLL MPLL Freq. 96 MHz SC32442B mpll Divide Divide 1/1 ~ 1/16 Counter Counter CAMCLKOUT Normally use mpll Schmit-triggere External d Level-shifter CAMIF Camera Processor CAMPCLK HCLK External MCLK Figure 23-5 CAMIF Clock Generation 4-pingpong Frame memory (SDRAM)
Page 492 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE MEMORY STORING METHOD The little-endian method in codec path is used to store in the frame memory. The pixels are stored from LSB to MSB side. AHB bus carries 32-bit word data. So, CAMIF makes each of the Y-Cb-Cr words in little-endian style. For preview path, two different formats exist.
Page 493 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE TIMING DIAGRAM FOR REGISTER SETTING The first register setting for frame capture command can occur anywhere in the frame period. But, it is recommended that you set it at the CAMVSYNC “L” state first and the CAMVSYNC information can be read from the status SFR (Please see next page).
Page 494 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE TIMING DIAGRAM FOR LAST IRQ IRQ except LastIRQ is generated before image capturing. Last IRQ which means capture-end can be set by following timing diagram. LastIRQEn is auto-cleared and ,as mentioned, SFR setting in ISR is for next frame command.
Page 495 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE CAMERA INTERFACE SPECIAL REGISTERS SOURCE FORMAT REGISTER Register Address Description Reset Value CISRCFMT 0x4F000000 Input Source Format Register CISRCFMT Description Initial State 0 = ITU-R BT.656 YCbCr 8-bit mode enable ITU601_656n [31] 1 = ITU-R BT.601 YCbCr 8-bit mode enable Cb,Cr Value Offset Control.
Page 496 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE WINDOW OPTION REGISTER Register Address Description Reset Value CIWDOFST 0x4F000004 Window Offset Register CIWDOFST Description Initial State 0 = No offset WinOfsEn [31] 1 = Window offset enable 0 = Normal ClrOvCoFiY [30] 1 = Clear the overflow indication flag of input CODEC FIFO Y Window Horizontal Offset (the number which is the horizontal pixels except WinHorOfst * 2, WinHorOfst...
Page 497 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE GLOBAL CONTROL REGISTER Register Address Description Reset Value CIGCTRL 0x4F000008 Global Control Register CIGCTRL Description Initial State SwRst [31] Camera Interface Software Reset CamRst [30] External Camera Processor Reset or Power Down Reserved [29] This bit is reserved and the value must be 1. This register should be set only at ITU-T 601 8-bit mode.
Page 498 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE Y3 START ADDRESS REGISTER Register Address Description Reset Value CICOYSC3 0x4F000020 frame start address for codec DMA CICOYSC3 Description Initial State CICOYSC3 [31:0] frame start address for codec DMA Y4 START ADDRESS REGISTER Register Address Description Reset Value CICOYSA4...
Page 499 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE CB4 START ADDRESS REGISTER Register Address Description Reset Value CICOCBSA4 0x4F000034 Cb 4 frame start address for codec DMA CICOCBSA4 Description Initial State CICOCBSA4 [31:0] Cb 4 frame start address for codec DMA CR1 START ADDRESS REGISTER Register Address Description...
Page 500 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE CODEC TARGET FORMAT REGISTER Register Address Description Reset Value CICOTRGFMT 0x4F000048 Target image format of codec DMA CICOTRGFMT Description Initial State 0 = YCbCr 4:2:0 codec scaler input image format. In this case, horizontal line decimation is performed before codec scaler. In422_Co [31] (normally used)
Page 501 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE CODEC DMA CONTROL REGISTER Register Address Description Reset Value CICOCTRL 0x4F00004C Codec DMA control related CICOCTRL Description Initial State Yburst1_Co [23:19] Main burst length for codec Y frames Yburst2_Co [18:14] Remained burst length for codec Y frames Cburst1_Co [13:9] Main burst length for codec Cb/Cr frames...
Page 502 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE REGISTER SETTING GUIDE FOR CODEC SCALER AND PREVIEW SCALER SRC_Width and DST_Width satisfy the word boundary constraints such that the number of horizontal pixel can be represented to kn where n = 1,2,3, … and k = 1 / 2 / 8 for 24bppRGB / 16bppRGB / YCbCr420 image, respectively.
Page 503 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE If ( SRC_Height >= 64 × DST_Height ) { Exit(-1); /* Out Of Vertical Scale Range */ } else if (SRC_Height >= 32 × DST_Height) { PreVerRatio_xx = 32; V_Shift = 5; } else if (SRC_Height >= 16 × DST_Height) { PreVerRatio_xx = 16; V_Shift = 4; } else if (SRC_Height >= 8 ×...
Page 504 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE CODEC MAIN-SCALER CONTROL REGISTER Register Address Description Reset Value CICOSCCTRL 0x4F000058 Codec main-scaler control CICOSCCTRL Description Initial State Codec scaler bypass for upper 2048 x 2048 size (In this case, ImgCptEn_CoSC and ImgCptEn_PrSC should be 0, but ImgCptEn should be 1.
Page 505 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE CODEC STATUS REGISTER Register Address Description Reset Value CICOSTATUS 0x4F000064 Codec path status CICOSTATUS Description Initial State OvFiY_Co [31] Overflow state of codec source FIFO Y OvFiCb_Co [30] Overflow state of codec source FIFO Cb OvFiCr_Co [29] Overflow state of codec source FIFO Cr...
Page 506 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE RGB3 START ADDRESS REGISTER Register Address Description Reset Value CIPRCLRSC3 0x4F000074 RGB 3 frame start address for preview DMA CIPRCLRSC3 Description Initial State CIPRCLRSC3 [31:0] RGB 3 frame start address for preview DMA RGB4 START ADDRESS REGISTER Register Address Description...
Page 507 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW DMA CONTROL REGISTER Register Address Description Reset Value CIPRCTRL 0x4F000080 Preview DMA control related CIPRCTRL Description Initial State RGBburst1_Pr [23:19] Main burst length for preview RGB frames RGBburst2_Pr [18:14] Remained burst length for preview RGB frames 0 = Normal LastIRQEn_Pr 1 = Enable last IRQ at the end of frame capture.
Page 508 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW PRE-SCALER CONTROL REGISTER 2 Register Address Description Reset Value CIPRSCPREDST 0x4F000088 Preview pre-scaler destination format CIPRSCPREDST Description Initial State PreDstWidth_Pr [27:16] Destination width for preview pre-scaler PreDstHeight_Pr [11:0] Destination height for preview pre-scaler PREVIEW MAIN-SCALER CONTROL REGISTER Register Address Description...
Page 509 SC32442B RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW STATUS REGISTER Register Address Description Reset Value CIPRSTATUS 0x4F000098 Preview path status CIPRSTATUS Description Initial State OvFiCb_Pr [31] Overflow state of preview source FIFO Cb OvFiCr_Pr [30] Overflow state of preview source FIFO Cr FrameCnt_Pr [27:26] Frame count of preview DMA FlipMd_Pr...
Page 510 SC32442B RISC MICROPROCESSOR BUS PRIORITIES BUS PRIORITIES OVERVIEW The bus arbitration logic determines the priorities of bus masters. It supports a combination of rotation priority mode and fixed priority mode. BUS PRIORITY MAP The SC32442B holds 13 bus masters. They include DRAM refresh controller, LCD_DMA, CAMIF DMA, DMA0, DMA1, DMA2, DMA3, USB_HOST_DMA, EXT_BUS_MASTER, Test interface controller (TIC) and ARM920T.
Page 511 BUS PRIORITIES SC32442B RISC MICROPROCESSOR NOTES 24-2...
Page 512: Electrical Data
SC32442B RISC MICROPROCESSOR ELECTRICAL DATA ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS Table 25-1 Absolute Maximum Rating Parameter Symbol Rating Unit 1.7V V DDiarm 1.2V V 3.3V V DDOP 3.3V V DDOP1 3.3V V DC Supply Voltage DDOP2 2.8V V DDOP3 1.8V V DDMOP 1.8V/2.5V/3.0V/3.3V V DDRTC...
Page 513 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR RECOMMENDED OPERATING CONDITIONS Table 25-2 Recommended Operating Conditions Rating Parameter Symbol Unit DDalive DC Supply Voltage for Alive Block 1.15 1.25 50MHz 0.95 1.25 66MHz 0.95 1.25 DDMPLL 100MHz 1.05 1.25 DDUPLL 125MHz 1.15 1.25 133MHz 1.15 1.25...
Page 514 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA Table25- 3 Normal I/O PAD DC Electrical Characteristics = -25 to 85 °C) Normal I/O PAD DC Electrical Characteristics for Memory (V = 1.8V±0.1V, T DDMOP Symbol Parameters Condition Typ. Unit High level input voltage LVCMOS interface 0.65V +0.3...
Page 515 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR = 3.3V ± 0.3V, T = -25 to 85 °C) DDOP, DDOP1, DDOP2, DDOP3 Symbol Parameters Condition Typ. Unit High level input voltage LVCMOS interface +0.3 Low level input voltage LVCMOS interface -0.3V Switching threshold 0.5V Schmitt trigger, positive-going threshold CMOS...
Page 516 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA = 2.8V ± 0.3V, T = -25 to 85 °C) DDOP1, DDOP2, DDOP3 Symbol Parameters Condition Typ. Unit High level input voltage LVCMOS interface 0.68*VDD +0.3 Low level input voltage LVCMOS interface -0.3 0.24*VDD Switching threshold 0.5V Schmitt trigger, positive-going threshold CMOS...
Page 517 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR Normal I/O PAD DC Electrical Characteristics for I/O = 2.5V ± 0.2V, T = -25 to 85 °C) DDOP2 Symbol Parameters Condition Typ. Unit High level input voltage LVCMOS interface 0.68*VDD +0.3 Low level input voltage LVCMOS interface -0.3 0.24*VDD...
Page 518 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA Table 25-4 USB DC Electrical Characteristics Symbol Parameter Condition Unit High level input voltage Low level input voltage High level input current Vin = 3.3V µA Low level input current Vin = 0.0V µA Static Output High 15K to GND Static Output Low 1.5K to 3.6V...
Page 519 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR A.C. ELECTRICAL CHARACTERISTICS XTALCYC 1/2 V 1/2 V NOTE: Clock input is from the X pin. TIpll Figure 25-1 XTIpll Clock Timing Diagram EXTCYC EXTHIGH EXTLOW 1/2 V 1/2 V NOTE: Clock input is from the EXTCLK pin. Figure 25-2 EXTCLK Clock Input Timing Diagram EXTCLK EX2HC...
Page 520 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA HCLK (internal) HC2CK CLKOUT (HCLK) HC2SCLK SCLK Figure 25-4 HCLK/CLKOUT/SCLK in case when EXTCLK is used EXTCLK RESW nRESET Figure 25-5 Manual Reset Input Timing Diagram 25-9...
Page 521 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR Power PLL can operate after OM[3:2] is latched. nRESET XTIpll or EXTCLK PLL is configured by S/W first time. tPLL Clock Disable VCO is adapted to new clock frequency. output tRST2RUN FCLK MCU operates by XTIpll FCLK is new frequency.
Page 522 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA E X T C L K X T Ip ll C lo c k D is a b le O S C 2 V C O O u tp u t S e v e ra l s lo w c lo c k s (X T Ip ll o r E X T C L K ) F C L K P o w e r_ O F F m o d e is in itia te d .
Page 523 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR Figure 25-8 ROM/SRAM Burst READ Timing Diagram (I) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=0, DW=16bit) 25-12...
Page 524 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA Figure 25-9 ROM/SRAM Burst READ Timing Diagram (II) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=1, DW=16bit) 25-13...
Page 525 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR HCLK tHZD ADDR 'HZ' tHZD 'HZ' tHZD 'HZ' tXnBRQH tXnBRQS XnBREQ tXnBACKD tXnBACKD XnBACK Figure 25-10 External Bus Request in ROM/SRAM Cycle (Tacs=0, Tcos=0, Tacc=8, Toch=0, Tcah=0, PMC=0, ST=0) 25-14...
Page 526 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA HCLK tRAD tRAD ADDR tRCD tRCD nGCSx Tacs Tcah tROD tROD Tcos Tacc Toch nWBEx tRDS DATA tRDH Figure 25-11 ROM/SRAM READ Timing Diagram (I) (Tacs=2,Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=0) 25-15...
Page 527 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR HCLK tRAD tRAD ADDR tRCD tRCD nGCSx Tacs Tcah tROD tROD Tcos Tacc Toch tRBED tRBED nBEx tRDS DATA tRDH Figure 25-12 ROM/SRAM READ Timing Diagram (II) (Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2cycle, PMC=0, ST=1) 25-16...
Page 528 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA HCLK tRAD tRAD ADDR tRCD tRCD nGCSx Tacs Tcah tRWD tRWD Tcos Tacc Toch tRWBED tRWBED nWBEx Tcos Toch tRDD tRDD DATA Figure 25-13 ROM/SRAM WRITE Timing Diagram (I) (Tacs=2,Tcos=2,Tacc=4,Toch=2, Tcah=2, PMC=0, ST=0 25-17...
Page 529 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR HCLK tRAD tRAD ADDR tRCD tRCD nGCSx Tacs Tcah tRWD tRWD Tcos Tacc Toch tRBED tRBED nBEx tRDD tRDD DATA Figure 25-14 ROM/SRAM WRITE Timing Diagram (II) (Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=1) 25-18...
Page 530 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA HCLK ADDR nGCSx Tacs delayed Tacc = 6cycle Tacs sampling nWait nWait DATA NOTE: The status of nWait is checked at (Tacc-1) cycle. Figure 25-15 External nWAIT READ Timing Diagram (Tacs=0, Tcos=0, Tacc=6, Toch=0, Tcah=0, PMC=0, ST=0) HCLK ADDR nGCSx...
Page 531 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR HCLK tRAD tRAD ADDR tRCD nGCSx Tacs tROD Tcos Tacc tRDS DATA tRDH Figure 25-17 Masked-ROM Single READ Timing Diagram (Tacs=2, Tcos=2, Tacc=8, PMC=01/10/11) HCLK tRAD tRAD tRAD tRAD tRAD tRAD ADDR tRCD nGCSx tROD Tacc Tpac Tpac...
Page 532 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA Figure 25-19 SDRAM Single Burst READ Timing Diagram (Trp=2, Trcd=2, Tcl=2, DW=16bit) 25-21...
Page 533 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR EXTCLK tHZD SCLK 'HZ' tHZD SCKE 'HZ' tHZD ADDR/BA 'HZ' tHZD A10/AP 'HZ' tHZD nGCSx 'HZ' tHZD nSRAS 'HZ' tHZD nSCAS 'HZ' tHZD nBEx 'HZ' tHZD 'HZ' tXnBRQH tXnBRQS tXnBRQL XnBREQ XnBACK tXnBACKD tXnBACKD Figure 25-20 External Bus Request in SDRAM Timing Diagram (Trp=2, Trcd=2, Tcl=2) 25-22...
Page 534 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA SCLK SCKE tSAD tSAD ADDR/BA tSAD A10/AP tSCSD tSCSD nGCSx tSRD tSRD nSRAS tSCD nSCAS nBEx tSWD tSWD DATA 'HZ' Figure 25-21 SDRAM MRS Timing Diagram 25-23...
Page 535 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR SCLK SCKE tSAD tSAD tSAD tSAD ADDR/BA tSAD tSAD A10/AP tSCSD tSCSD tSCSD nGCSx tSRD tSRD nSRAS Trcd tSCD nSCAS tSBED nBEx tSWD tSDS DATA tSDH Figure 25-22 SDRAM Single READ Timing Diagram (I) (Trp=2, Trcd=2, Tcl=2) 25-24...
Page 536 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA SCLK SCKE tSAD tSAD tSAD tSAD ADDR/BA tSAD tSAD A10/AP tSCSD tSCSD tSCSD nGCSx tSRD tSRD nSRAS Trcd tSCD nSCAS tSBED nBEx tSWD tSDS DATA tSDH Figure 25-23 SDRAM Single READ Timing Diagram (II) (Trp=2, Trcd=2, Tcl=3) 25-25...
Page 537 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR SCLK SCKE tSAD tSAD ADDR/BA tSAD A10/AP tSCSD tSCSD nGCSx tSRD tSRD nSRAS tSCD nSCAS nBEx tSWD DATA 'HZ' NOTE: Before executing an auto/self refresh command, all the banks must be in idle state. Figure 25-24 SDRAM Auto Refresh Timing Diagram (Trp=2, Trc=4) 25-26...
Page 538 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA Figure 25- 25 SDRAM Page Hit-Miss READ Timing Diagram (Trp=2, Trcd=2, Tcl=2) 25-27...
Page 539 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR SCLK tCKED tCKED SCKE tSAD tSAD ADDR/BA tSAD A10/AP tSCSD tSCSD nGCSx tSRD tSRD nSRAS tSCD nSCAS nBEx tSWD DATA 'HZ' 'HZ' NOTE: Before executing an auto/self refresh command, all the banks must be in idle state. Figure 25-26 SDRAM Self Refresh Timing Diagram (Trp=2, Trc=4) 25-28...
Page 540 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA SCLK SCKE tSAD tSAD tSAD tSAD ADDR/BA tSAD tSAD A10/AP tSCSD tSCSD tSCSD nGCSx tSRD tSRD nSRAS Trcd tSCD nSCAS tSBED nBEx tSWD tSWD tSDD DATA tSDD Figure 25-27 SDRAM Single Write Timing Diagram (Trp=2, Trcd=2) 25-29...
Page 541 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR Figure 25-28 SDRAM Page Hit-Miss Write Timing Diagram (Trp=2, Trcd=2, Tcl=2) 25-30...
Page 542 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA XSCLK tXRS XnXDREQ tXRS tXAD tCADH XnXDACK Read Write Min. 3SCLK tCADL Figure 25-29 External DMA Timing Diagram (Handshake, Single transfer) Tf2hsetup VSYNC Tf2hhold HSYNC Tvfpd Tvspw Tvbpd VDEN HSYNC Tl2csetup Tvclkh Tvclk VCLK Tvclkl Tvdhold Tvdsetup Tve2hold...
Page 543 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR IISSCLK tLRCK IISLRCK (out) tSDO IISLRCK (out) tSDIS tSDIH IISSDI (in) Figure 25-31 IIS Interface Timing Diagram fSCL tSCLHIGH tSCLLOW IICSCL tSTOPH tBUF tSDAS tSDAH tSTARTS IICSDA Figure 25-32 IIC Interface Timing Diagram 25-32...
Page 544 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA SDCLK tSDCD SDCMD (out) tSDCS tSDCH SDCMD (in) tSDDD SDDATA[3:0] (out) tSDDS tSDDH SDDATA[3:0] (in) Figure 25-33 SD/MMC Interface Timing Diagram SPICLK tSPIMOD SPIMOSI (MO) tSPISIS tSPISIH SPIMOSI (SI) tSPISOD SPIMISO (SO) tSPIMIS tSPIMIH SPIMISO (MI) Figure 25-34 SPI Interface Timing Diagram (CPHA=1, CPOL=1) 25-33...
Page 545 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR TACLS TWRPH0 TWRPH1 TACLS TWRPH0 TWRPH1 HCLK HCLK tCLED tCLED tALED tALED tWED tWED tWED tWED nFWE nFWE tWDS tWDH tWDS tWDH DATA[7:0] COMMAND DATA[7:0] ADDRESS Figure 25-35 NAND Flash Address/Command Timing Diagram TWRPH0 TWRPH1 TWRPH0 TWRPH1 HCLK...
Page 546 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA PCLK VSYNC TssVsync ThVsync PCLK HREF TssHref ThHref PCLK DATA TssData ThData Figure 25-37 Camera Timing Diagram 25-35...
Page 547 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR Table 25-5 Clock Timing Constants = 1.7V ± 0.05 V, V = 1.2V ± 0.05 V, T = -25 to 85 °C, V = 3.3V ± 0.3V) DDiarm DDMOP Parameter Symbol Unit Crystal clock input frequency –...
Page 548 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA Table 25-6 ROM/SRAM Bus Timing Constants = 1.7V ± 0.05 V, V = 1.2V ± 0.05 V, T = -25 to 85 °C, V = 1.8V ± 0.1V) DDiarm DDMOP Parameter Symbol Unit = 1.8V) = 1.8V) DDMOP DDMOP...
Page 549 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR = 1.7V ± 0.05 V, T = -25 to 85 °C, V = 1.8V ± 0.1V, 125MHz, CL=25pF) DDi, DDiarm DDMOP Parameter Symbol Unit SDRAM Address Delay 1.50 – 5.17 SDRAM Chip Select Delay 1.57 –...
Page 550 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA Table 25-8 External Bus Request Timing Constants = 1.7V ± 0.05 V, V = 1.2V ± 0.05 V, T = -25 to 85 °C, V = 3.3V ± 0.3V) DDiarm Parameter Symbol Typ. Unit External Bus Request Setup Time –...
Page 551 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR Table 25-10 TFT LCD Controller Module Signal Timing Constants = 1.7V ± 0.05 V, V = 1.2V ± 0.05 V, T = -25 to 85 °C, V = 3.3V ± 0.3V) DDiarm Parameter Symbol Units (note1) Vertical Sync Pulse Width Tvspw...
Page 552 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA Table 25-12 IIC BUS Controller Module Signal Timing = 1.7V ± 0.05 V, V = 1.2V ± 0.05 V, T = -25 to 85 °C, V = 3.3V ± 0.3V) DDiarm Parameter Symbol Typ. Unit std.
Page 553 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR Table 25-14 SPI Interface Transmit/Receive Timing Constants = 1.7V ± 0.05 V, V = 1.2V ± 0.05 V, T = -25 to 85 °C, V = 3.3V ± 0.3V) DDiarm Parameter Symbol Typ. Unit SPI MOSI Master Output Delay Time –...
Page 554 SC32442B RISC MICROPROCESSOR ELECTRICAL DATA Table 25-16 USB Full Speed Output Buffer Electrical Characteristics = 1.7V ± 0.05 V, V = 1.2V ± 0.05 V, T = -25 to 85 °C, V = 3.3V ± 0.3V) DDiarm Parameter Symbol Condition Unit Driver Characteristics Transition Time...
Page 555 ELECTRICAL DATA SC32442B RISC MICROPROCESSOR Table 25-18 NAND Flash Interface Timing Constants = 1.7V ± 0.05 V, V = 1.2V ± 0.05 V , T = -25 to 85 °C, V = 1.8V ± 0.1V) DDiarm DDMOP Parameter Symbol Unit = 1.8V) = 1.8V) DDMOP...
Page 556 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
Page 557: Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.
Page 558: Address Configuration
The Mobile SDRAM is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle.
Page 559: Pin Configuration
K5D2G13ACM-D075 MCP MEMORY PIN CONFIGURATION DQ4d DQ5d DQ1d DQ6d DQM1d RASd A12d BA1d DQ9d DQ10d /IO4n /IO5n /IO1n /IO6n DQ2d DQ0d DQ3d DQ7d A11d CKEd DQM3d CASd A10d BA0d DQ8d DQ11d DQ12d /IO2n /IO0n /IO3n /IO7n DQ14d DQ13d DQ17d DQ15d DQM2d DQ19d DQ16d...
Page 560: Pin Description
Pin Function VSSQd DQ Ground No Connection ORDERING INFORMATION K 5 D 2G 13 A C M - D 0 75 Samsung MCP Memory(2chips) M-SDR Speed 75 : 7.5ns (133MHz@CL3) Device Type NAND Flash Speed NAND Flash + Mobile SDRAM...
Page 561 K5D2G13ACM-D075 MCP MEMORY FUNCTIONAL BLOCK DIAGRAM VSSn VCCn 2Gb NAND Flash Memory ALEn CLEn R/Bn DQ0/IO0 to DQ7/IO7 VDDd VDDQd VSSd VSSQd CLKd CKEd RASd 512Mb Mobile CASd SDRAM DQ8 to DQ31 A0d~A12d BA0d~BA1d DQM0d~DQM3d Revision 1.0 December 2006...
Page 562 K5D2G13ACM-D075 MCP MEMORY 2Gb(256Mb x8) NAND Flash Memory A-Die Revision 1.0 December 2006...
Page 563 K5D2G13ACM-D075 MCP MEMORY Figure 1. Functional Block Diagram 2,048M + 64M Bit X-Buffers NAND Flash Latches ARRAY & Decoders (2,048 + 64)Byte x 131,072 Y-Buffers Latches & Decoders Data Register & S/A Y-Gating Command Command Register I/O Buffers & Latches Control Logic &...
Page 564: Product Introduction
K5D2G13ACM-D075 MCP MEMORY Product Introduction The device is a 2,112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations.
Page 565 K5D2G13ACM-D075 MCP MEMORY ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit -0.6 to +2.45 Voltage on any pin relative to VSS -0.6 to +2.45 -0.6 to Vcc + 0.3 (< 2.45V) °C Temperature Under Bias -40 to +125 BIAS °C Storage Temperature -65 to +150 Short Circuit Current NOTE :...
Page 566 K5D2G13ACM-D075 MCP MEMORY VALID BLOCK Parameter Symbol Typ. Unit 2,008 2,048 Blocks NOTE : 1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro- gram factory-marked bad blocks.
Page 567 K5D2G13ACM-D075 MCP MEMORY Program / Erase Characteristics Parameter Symbol Unit µs Program Time PROG µs Dummy Busy Time for Two-Plane Page Program DBSY Number of Partial Program Cycles cycles Block Erase Time BERS NOTE : 1. Typical value is measured at Vcc=3.3V, T =25°C.
Page 568 K5D2G13ACM-D075 MCP MEMORY AC Characteristics for Operation Parameter Symbol Unit µs Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time CE Access Time RE High to Output Hi-Z CE High to Output Hi-Z...
Page 569 All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini- tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048.
Page 570 K5D2G13ACM-D075 MCP MEMORY NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done.
Page 571 K5D2G13ACM-D075 MCP MEMORY NAND Flash Technical Notes (Continued) Erase Flow Chart Read Flow Chart Start Start Write 60h Write 00h Write Block Address Write Address Write D0h Write 30h Read Data Read Status Register ECC Generation I/O 6 = 1 ? or R/B = 1 ? Verify ECC Reclaim the Error...
Page 572 K5D2G13ACM-D075 MCP MEMORY NAND Flash Technical Notes (Continued) Copy-Back Operation with EDC & Sector Definition for EDC Generally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors.
Page 573 K5D2G13ACM-D075 MCP MEMORY System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of µ-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption.
Page 574 K5D2G13ACM-D075 MCP MEMORY NOTE DATA ADDRESS Device I/Ox Data In/Out Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 I/O 0 ~ I/O 7 2,112byte A0~A7 A8~A11 A12~A19 A20~A27 Command Latch Cycle I/Ox Command Address Latch Cycle I/Ox Col. Add2 Row Add1 Col.
Page 575 K5D2G13ACM-D075 MCP MEMORY Input Data Latch Cycle I/Ox DIN final DIN 0 DIN 1 * Serial Access Cycle after Read (CLE=L, WE=H, ALE=L) RHOH I/Ox Dout Dout Dout NOTES : Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
Page 576 K5D2G13ACM-D075 MCP MEMORY Serial Access Cycle after Read (EDO Type, CLE=L, WE=H, ALE=L) RHOH RLOH I/Ox Dout Dout NOTES : Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. tRLOH is valid when frequency is higher than 33MHz. tRHOH starts to be valid when frequency is lower than 33MHz.
Page 577 K5D2G13ACM-D075 MCP MEMORY Read Operation I/Ox Dout N+1 Dout M Col. Add2 Row Add1 Row Add2 Dout N Col. Add1 Row Add3 Column Address Row Address Busy Read Operation (Intercepted by CE) Dout N+2 I/Ox Col. Add2 Row Add1 Row Add2 Row Add3 Dout N Dout N+1...
Page 578 K5D2G13ACM-D075 MCP MEMORY Revision 1.0 December 2006...
Page 579 K5D2G13ACM-D075 MCP MEMORY Page Program Operation PROG I/Ox Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3 SerialData Program 1 up to m Byte Read Status Column Address Row Address Input Command Command Serial Input Command =0 Successful Program =1 Error in Program NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
Page 580 K5D2G13ACM-D075 MCP MEMORY Revision 1.0 December 2006...
Page 581 K5D2G13ACM-D075 MCP MEMORY Revision 1.0 December 2006...
Page 582 K5D2G13ACM-D075 MCP MEMORY Block Erase Operation BERS I/Ox I/O 0 Row Add1 Row Add2 Row Add3 Row Address Busy Auto Block Erase Erase Command =0 Successful Erase Read Status =1 Error in Erase Setup Command Command Revision 1.0 December 2006...
Page 583 K5D2G13ACM-D075 MCP MEMORY Revision 1.0 December 2006...
Page 584 K5D2G13ACM-D075 MCP MEMORY Revision 1.0 December 2006...
Page 585 K5D2G13ACM-D075 MCP MEMORY Read ID Operation I/Ox Device 3rd cyc. 4th cyc. 5th cyc. Code Read ID Command Maker Code Device Code Address 1cycle Device Device Code (2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle 1.8V Revision 1.0 December 2006...
Page 586 K5D2G13ACM-D075 MCP MEMORY ID Definition Table 90 ID : Access command = 90H Description Byte Maker Code Byte Device Code Byte Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum Byte Plane Number, Plane Size Byte...
Page 587 K5D2G13ACM-D075 MCP MEMORY 5th ID Data Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Plane Number 64Mb 128Mb 256Mb Plane Size 512Mb (w/o redundant Area) Reserved Revision 1.0 December 2006...
Page 588 K5D2G13ACM-D075 MCP MEMORY Device Operation PAGE READ Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 25µs(t ).
Page 589 K5D2G13ACM-D075 MCP MEMORY Figure 7. Random Data Output In a Page Address Address I/Ox Data Output Data Output 5Cycles 2Cycles Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2 Data Field Data Field Spare Field Spare Field PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 2,112, in a single page program cycle.
Page 590 K5D2G13ACM-D075 MCP MEMORY Figure 9. Random Data Input In a Page PROG "0" I/Ox Pass Address & Data Input Address & Data Input I/O0 Col. Add.1,2 Col. Add.1,2 & Row Add1,2,3 "1" Data Data Fail Note: 1. For EDC operation, only one time random data input is possible at the same address. Copy-Back Program The Copy-Back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.
Page 591 K5D2G13ACM-D075 MCP MEMORY EDC OPERATION Note that for the user who use Copy-Back with EDC mode, only one time random data input is possible at the same address during Copy-Back program or page program mode. For the user who use Copy-Back without EDC, there is no limitation for the random data input at the same address.
Page 592 K5D2G13ACM-D075 MCP MEMORY Figure 14. Two-Plane Page Program DBSY PROG 0 ~ 7 Address & Data Input Address & Data Input Note* Valid Valid 11 : 11 : Fixed ’Low’ Valid 17 : 17 : Fixed ’Low’ Fixed ’High’ Fixed ’Low’ Valid 28 : 28 :...
Page 593 K5D2G13ACM-D075 MCP MEMORY Two-Plane Copy-Back Program Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 2112 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous program- ming of two pages.
Page 594 K5D2G13ACM-D075 MCP MEMORY Figure 17. Two-Plane Copy-Back Program Operation with Random Data Input I/Ox Add.(5Cycles) Add.(5Cycles) Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2 & Row Add.1,2,3 Source Address On Plane0 Source Address On Plane1 DBSY I/Ox Add.(5Cycles) Data Add.(2Cycles) Data Note4 Col.
Page 595 K5D2G13ACM-D075 MCP MEMORY READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last.
Page 596 K5D2G13ACM-D075 MCP MEMORY Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it.
Page 597 K5D2G13ACM-D075 MCP MEMORY READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading.
Page 598 K5D2G13ACM-D075 MCP MEMORY Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V. WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down.
Page 599 K5D2G13ACM-D075 MCP MEMORY 512Mb(16Mb x32) Mobile SDRAM C-Die Revision 1.0 December 2006...
Page 600: Functional Block Diagram
K5D2G13ACM-D075 MCP MEMORY FUNCTIONAL BLOCK DIAGRAM Data Input Register LDQM Bank Select 4M x 32 4M x 32 4M x 32 4M x 32 Column Decoder Latency & Burst Length LCKE Programming Register LRAS LCBR LCAS LWCBR LDQM Timing Register Revision 1.0 December 2006...
Page 601 K5D2G13ACM-D075 MCP MEMORY ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to V -1.0 ~ 2.6 Voltage on V supply relative to V -1.0 ~ 2.6 °C Storage temperature -55 ~ +150 Power dissipation Short circuit current NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Page 602 K5D2G13ACM-D075 MCP MEMORY DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to V = 0V, T = -25 to 85°C) Parameter Symbol Test Condition 133Mhz@CL3 Unit Note Burst length = 1 Operating Current ≥ t (min) (One Bank Active) = 0 mA CKE ≤...
Page 603 K5D2G13ACM-D075 MCP MEMORY AC OPERATING TEST CONDITIONS = 1.7 ~ 1.95 V, T = -25 ~ 85°C) Parameter Value Unit AC input levels (Vih/Vil) 0.9 x V / 0.2 Input timing measurement reference level 0.5 x V Input rise and fall time tr/tf = 1/1 Output timing measurement reference level 0.5 x V...
Page 604 K5D2G13ACM-D075 MCP MEMORY OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol 133Mhz@CL3 Unit Note Row active to row active delay (min) RAS to CAS delay (min) 22.5 Row precharge time (min) 22.5 (min) Row active time (max) Row cycle time (min) 72.5...
Page 605 K5D2G13ACM-D075 MCP MEMORY AC CHARACTERISTICS (AC operating conditions unless otherwise noted) 133Mhz@CL3 Parameter Symbol Unit Note CLK cycle time CAS latency=3 1000 CLK to valid output delay CAS latency=3 Output data hold time CAS latency=3 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z...
Page 606 K5D2G13ACM-D075 MCP MEMORY SIMPLIFIED TRUTH TABLE A12,11, COMMAND CKEn-1 CKEn DQM BA0,1 A10/AP Note A9 ~ A0 Register Mode Register Set OP CODE 1, 2 Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Row Address Read & Auto Precharge Disable Column Column Address...
Page 607 K5D2G13ACM-D075 MCP MEMORY A. MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with Normal MRS BA0 ~ BA1 Address A12 ~ A10/AP "0" Setting for Function W.B.L Test Mode CAS Latency Burst Length Normal MRS Normal MRS Mode Test Mode CAS Latency Burst Type Burst Length...
Page 608 K5D2G13ACM-D075 MCP MEMORY Partial Array Self Refresh 1. In order to save power consumption, Mobile SDR SDRAM has PASR option. 2. Mobile SDR SDRAM supports 3 kinds of PASR in self refresh mode : Full array, 1/2 array, 1/4 array BA1=0 BA1=0 BA1=0...
Page 609 K5D2G13ACM-D075 MCP MEMORY C. BURST SEQUENCE 1. BURST LENGTH = 4 Initial Address Sequential Interleave 2. BURST LENGTH = 8 Initial Address Sequential Interleave Revision 1.0 December 2006...
Page 610 K5D2G13ACM-D075 MCP MEMORY A. DEVICE OPERATIONS ADDRESSES of 64Mb ADDRESSES of 128Mb BANK ADDRESSES (BA0 ~ BA1) BANK ADDRESSES (BA0 ~ BA1) : In case x 16 : In case x 16 This Mobile SDR SDRAM is organized as four independent This Mobile SDR SDRAM is organized as four independent banks of 2,097,152 words x 16 bits memory arrays.
Page 611 K5D2G13ACM-D075 MCP MEMORY A. DEVICE OPERATIONS (continued) ADDRESSES of 256Mb ADDRESSES of 512Mb BANK ADDRESSES (BA0 ~ BA1) BANK ADDRESSES (BA0 ~ BA1) : In case x 16 1/CS : In case x 16 This Mobile SDR SDRAM is organized as four independent This Mobile SDR SDRAM is organized as four independent banks of 8,388,608 words x 16 bits memory arrays.
Page 612: Nop And Device Deselect
K5D2G13ACM-D075 MCP MEMORY A. DEVICE OPERATIONS (continued) CLOCK (CLK) DQM OPERATION The clock input is used as the reference for all Mobile SDR The DQM is used to mask input and output operations. It works SDRAM operations. All operations are synchronized to the posi- similar to OE during read operation and inhibits writing during tive going edge of the clock.
Page 613 K5D2G13ACM-D075 MCP MEMORY A. DEVICE OPERATIONS (continued) EXTENDED MODE REGISTER SET (EMRS) BANK ACTIVATE. The bank activate command is used to select a random row in an 1. For Internal TCSR, PASR and DS support idle bank. By asserting low on RAS and CS with desired row and The extended mode register stores the data for selecting driver bank address, a row access is initiated.
Page 614: Burst Read
K5D2G13ACM-D075 MCP MEMORY A. DEVICE OPERATIONS (continued) PRECHARGE BURST READ The precharge operation is performed on an active bank by The burst read command is used to access burst of data on con- asserting low on CS, RAS, WE and A10/AP with valid BA0 ~ BA1 secutive clock cycles from an active row in an active bank.
Page 615 K5D2G13ACM-D075 MCP MEMORY A. DEVICE OPERATIONS (continued) SELF REFRESH The self refresh is another refresh mode available in the Mobile SDR SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of Mobile SDR SDRAM. In self refresh mode, the Mobile SDR SDRAM disables the internal clock and all the input buffers except CKE.
Page 616 K5D2G13ACM-D075 MCP MEMORY B. BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 1) Clock Suspended During Write (BL=4) 2) Clock Suspended During Read (BL=4) Masked by CKE Masked by CKE Internal Internal DQ(CL2) DQ(CL2) DQ(CL3) DQ(CL3) Not Written Suspended Dout 2.
Page 617 K5D2G13ACM-D075 MCP MEMORY 3. CAS Interrupt (I) 1) Read interrupted by Read (BL=4) DQ(CL2) DQ(CL3) 2) Write interrupted by Write (BL=2) 3) Write interrupted by Read (BL=2) WR WR DQ(CL2) DQ(CL3) Note: 1) "Interrupt" : burst read/write is to stopped by external command before the end of burst. "CAS Interrupt"...
Page 618 K5D2G13ACM-D075 MCP MEMORY 4. CAS Interrupt (II) : Read Interrupted by Write & DQM (a) CL=2, BL=4 i) CMD ii) CMD Hi-Z iii) CMD Hi-Z iv) CMD Hi-Z (b) CL=3, BL=4 i) CMD ii) CMD iii) CMD iv) CMD Hi-Z v) CMD Hi-Z Note:...
Page 619 The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal 4) tDAL defined Last data in to Active delay. SAMSUNG can support tDAL=tRDL+ tRP . Revision 1.0...
Page 620 2CLK Note: Mobile SDR SDRAM 1) SAMSUNG support tRDL=2 CLK(or 15ns) for 2) tBDL : 1 CLK ; Last data in to burst stop delay. Read or write burst stop command is valid at every burst length. 3) Number of valid output data after row precharge or burst stop :A, B for CAS latency= 2, 3 respectively.
Page 621 K5D2G13ACM-D075 MCP MEMORY 10. Clock Suspend Exit & Power Down Exit 1) Clock Suspend (=Active Power Down) Exit 2) Power Down (=Precharge Power Down) Exit Internal Internal NOP ACT 11. Auto Refresh & Self Refresh Auto Refresh An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock(CLK).
Page 622 K5D2G13ACM-D075 MCP MEMORY 12. About Burst Type Control At MRS A = "0". See the BURST SEQUENCE TABLE. (BL=4, 8) Sequential Counting BL=1, 2, 4, 8 and full page. Basic MODE At MRS A = "1". See the BURST SEQUENCE TABLE. (BL=4, 8) Interleave Counting At BL=1, 2 Interleave Counting = Sequential Counting.
Page 623 K5D2G13ACM-D075 MCP MEMORY C. FUNCTION TRUTH TABLE (TABLE 1) Current Address Action Note State ILLEGAL CA, A /AP ILLEGAL IDLE Row (& Bank) Active ; Latch RA Auto Refresh or Self Refresh OP code OP code Mode Register Access ILLEGAL CA, A /AP Begin Read ;...
Page 624 K5D2G13ACM-D075 MCP MEMORY C. FUNCTION TRUTH TABLE (TABLE 1, Continued) Current Address Action Note NOP --> Idle after t NOP --> Idle after t ILLEGAL Precharging ILLEGAL ILLEGAL NOP --> Idle after t ILLEGAL NOP --> Row Active after t NOP -->...
Page 625 K5D2G13ACM-D075 MCP MEMORY C. FUNCTION TRUTH TABLE (TABLE 2) Current Address Action Note State (n-1) Exit Self Refresh --> Idle after ts (ABI) Exit Self Refresh --> Idle after ts (ABI) Exit Self Refresh --> Idle after ts (ABI) Self ILLEGAL Refresh ILLEGAL...
Page 626 K5D2G13ACM-D075 MCP MEMORY Power Up Sequence Single Bit Read - Write - Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK Page Read Cycle at Different Bank @Burst Length=4 Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK Read &...
Page 627 K5D2G13ACM-D075 MCP MEMORY Power Up Sequence for EMRS(VDD 1.8V, PASR & Internal TCSR & DS) Support CLOCK ADDR A10/AP Hi-Z Hi-Z High level is necessary Precharge Auto Auto Normal Extended Row Active (All Bank) Refresh Refresh (A-Bank) : Don’t care Note: 1) Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
Page 628 K5D2G13ACM-D075 MCP MEMORY Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 CLOCK HIGH Note 1) ADDR Note 2) Note 2,3) Note 2,3) Note 2,3) Note 4) Note 2) BA0,BA1 Note 3) Note 3) Note 3) Note 4) A10/AP Hi-Z Row Active Read Write...
Page 629 K5D2G13ACM-D075 MCP MEMORY Note: 1) All input except CKE & DQM can be ’don't care’ when CS is high at the CLK high going edge. 2) Bank active & read/write are controlled by BA0,BA1. 64Mb/128Mb 256Mb/512Mb Active & Read/Write Bank A Bank B Bank C Bank D...
Page 630 K5D2G13ACM-D075 MCP MEMORY Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK CLOCK HIGH RC Note 1) Note 2) ADDR A10/AP Hi-Z CL=2 Note 3) Hi-Z CL=3 Note 3) CL=2 CL=3 Row Active Read Precharge Row Active Write Precharge (A-Bank) (A-Bank) (A-Bank)
Page 631 K5D2G13ACM-D075 MCP MEMORY Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK CLOCK HIGH Note 2) ADDR A10/AP Hi-Z CL=2 Note 4) Hi-Z CL=3 Note 1) Note 3) CL=2 Note 1) Note 3) CL=3 Row Active Read Read Write Write Precharge...
Page 632 K5D2G13ACM-D075 MCP MEMORY Page Read Cycle at Different Bank @Burst Length=4 CLOCK HIGH Note 1) Note 2) ADDR A10/AP CL=2 Hi-Z QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 CL=3 QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 Hi-Z CL=2 CL=3...
Page 633 K5D2G13ACM-D075 MCP MEMORY Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK CLOCK HIGH Note 2) ADDR RDd CCc A10/AP Hi-Z DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2 Note 1) Row Active Write Write Row Active Write Precharge...
Page 634 K5D2G13ACM-D075 MCP MEMORY Read & Write Cycle at Different Bank @Burst Length=4 CLOCK HIGH ADDR A10/AP Note 1) Hi-Z CL=2 QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 QBc0 QBc1 QBc2 Hi-Z CL=3 QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 QBc0 QBc1 CL=2 CL=3...
Page 635 K5D2G13ACM-D075 MCP MEMORY Read & Write Cycle with Auto Precharge I @Burst Length=4 CLOCK HIGH ADDR A10/AP CL=2 Hi-Z QBb3 QAa0 QAa1 QBb0 QBb1 QBb2 DAc0 DAc1 CL=3 Hi-Z QAa0 QAa1 QBb0 QBb1 QBb2 QBb3 DAc0 DAc1 CL=2 CL=3 Row Active Read with Read without Auto Precharge...
Page 636 K5D2G13ACM-D075 MCP MEMORY Read & Write Cycle with Auto Precharge II @Burst Length=4 CLOCK HIGH ADDR A10/AP CL=2 Hi-Z CL=3 Hi-Z CL=2 CL=3 Note1) Auto Precharge Row Active Read with Read with Auto Precharge Start Point (A-Bank) Auto Precharge Auto Precharge Start Point (B-Bank) (A-Bank)
Page 637 K5D2G13ACM-D075 MCP MEMORY Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4 CLOCK ADDR A10/AP Hi-Z Note 1) Row Active Read Clock Read Read DQM Write Write Suspension Write Clock Suspension : Don’t care Note: 1) DQM is needed to prevent bus contention. Revision 1.0 December 2006...
Page 638 K5D2G13ACM-D075 MCP MEMORY Read Interrupted by Precharge & Read Burst Stop Cycle @Full Page Burst CLOCK HIGH ADDR A10/AP CL=2 Hi-Z QAa0 QAa1 QAa2 QAa3 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 CL=3 QAa0 QAa1 QAa2 QAa3 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 Hi-Z CL=2...
Page 639 K5D2G13ACM-D075 MCP MEMORY Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=2CLK CLOCK HIGH ADDR A10/AP Note 1) Note 1,2) Hi-Z DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 Row Active Write Burst Stop Write...
Page 640 K5D2G13ACM-D075 MCP MEMORY Burst Read Single bit Write Cycle @Burst Length=2 CLOCK HIGH Note 2) ADDR A10/AP Hi-Z CL=2 DAa0 QAb0 QAb1 DBc0 QCd0 QCd1 Hi-Z CL=3 DAa0 QAb0 QAb1 DBc0 QCd0 QCd1 CL=2 CL=3 Precharge Row Active Row Active Row Active Read (C-Bank)
Page 641 K5D2G13ACM-D075 MCP MEMORY Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4 CLOCK Note 1) Note 2) Note 2) Note 3) ADDR BA0,BA1 A10/AP Hi-Z Precharge Row Active Read Precharge Power-down Entry Precharge Active Active Power-down Power-down Power-down Exit Entry Exit : Don’t care Note: 1) All banks should be in idle state prior to entering precharge power down mode.
Page 642 K5D2G13ACM-D075 MCP MEMORY Self Refresh Entry & Exit Cycle Refresh Entry & Exit Cycle CLOCK Note 2) Note 4) SRFX Note 1) Note 6) Note 3) ADDR BA0,BA1 A10/AP Hi-Z Hi-Z Self Refresh Entry Self Refresh Exit Auto Refresh : Don’t care Note: TO ENTER SELF REFRESH MODE 1) CS, RAS &...
Page 643 K5D2G13ACM-D075 MCP MEMORY Mode Register Set Cycle Auto Refresh Cycle CLOCK HIGH HIGH Note2) ARFC Note1) Note3) ADDR Hi-Z Hi-Z New Command Auto Refresh New Command : Don’t care Note: MODE REGISTER SET CYCLE 1) CS, RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register. 2) Minimum 2 clock cycles should be met before new RAS activation.
Page 644 K5D2G13ACM-D075 MCP MEMORY Extended Mode Register Set Cycle CLOCK HIGH Note2) Note1) Note3) ADDR Hi-Z EMRS New Command : Don’t care Note: EXTENDED MODE REGISTER SET CYCLE 1) CS, RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register. 2) Minimum 2 clock cycles should be met before new RAS activation.
Page 645 K5D2G13ACM-D075 MCP MEMORY PACKAGE DIMENSION 119-Ball Fine pitch Ball Grid Array Package (measured in millimeters) 14.00 ± 0.10 #A1 INDEX MARK 0.80 x 16 = 12.80 14.00 ± 0.10 (Datum B) (Datum A) 0.80 6.40 <TOP VIEW> 119-∅0.50 ± 0.05 <BOTTOM VIEW>...
Page 646: Mechanical Data
SC32442B RISC MICROPROCESSOR MECHANICAL DATA MECHANICAL DATA PACKAGE DIMENSIONS 14.000 Figure 1-1. 332-FBGA-SC32442B Package Dimension (Top View)
Page 647 MECHANICAL DATA SC32442B RISC MICROPROCESSOR 0.500 x 25 = 12.500 0.500 332-0.300±0.05 Figure 1-2. 332-FBGA SC32442B Package Dimension (Bottom View)

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