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RESET
SUMMARY TABLE OF BACK-UP MODE, STOP MODE, AND RESET STATUS
For more understanding, please see the below description Table 8-7.
Item/Mode
•
Approach
External nRESET pin is low
Condition
level state or V
than V
•
Port status
All I/O port is floating status
except for P3.2 and P3.3
•
All port becomes input
mode
but is blocked.
•
Disable all pull-up resister
except for P3.2 and P3.3
•
Control
All control register and
Register
system register are
initialized as list of Table 8-3.
•
Releasing
External nRESET pin is
Condition
high
(rising edge).
•
The rising edge of LVD
circuit is generated.
•
Others
There is no current
consumption in chip.
8-20
Table 8-7. Summary of Each Mode
Back-up
•
is lower
DD
LVD
Reset Status
External nRESET pin is on
rising edge.
•
The rising edge at VDD is
detected by LVD circuit.
(When VDD ≥ V
)
LVD
•
Watch-dog timer overflow
signal is activated.
•
All I/O port is floating status
except P3.2 and P3.3.
•
Disable all pull-up resister
except P3.2 and P3.3.
•
All control register and
system register are initialized
as list of Table 8-3.
•
After passing an oscillation
warm-up time
•
There can be input leakage
current in chip.
Stop
STOPCON ← # A5H
•
STOP
( LD STOPCON,#0A5H )
( STOP)
•
All port is keep the previous
status.
•
Output port data is not
changed.
–
•
External interrupt, or reset
•
SED & R Circuit.
•
It depends on control
program
S3F80JB
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