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2
S3C2501X
I
C CONTROLLER
6.4.4 DATA VALIDITY
The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line
can only change when clock signal on the SCL line is low.
6.4.5 START AND STOP CONDITIONS
Start and stop conditions are always generated by the master. The bus is considered to be busy after the start
condition is generated. The bus is considered to be free again when a brief time interval has elapsed following
the stop condition.
— Start condition: a High-to-Low transition of the SDA line while SCL is high.
— Stop condition: a Low-to-High transition of the SDA line while SCL is high.
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
P
Start
Stop
Address
R/W
ACK
DATA
ACK
DATA
ACK
Condition
Condition
Figure 6-4. Start and Stop Conditions
6-5
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