Clock Status Register; Ahb Bus Master Priority Register - Samsung S3C2501X User Manual

S3C2501X
4.8.5 CLOCK STATUS REGISTER (CLKST)
The operating frequency of the S3C2501X can be obtained by reading the CLKST register. The CPU Freq field in
CLKST[11:0] decodes the CPU_FREQ[2:0] settings and the BUS Freq in CLKST[23:12] decodes the
BUS_FREQ[2:0] settings. There are 3 clock modes in the S3C2501X - fast mode, sync mode and async mode. In
async mode, there is no misinformation about the frequency. But Care must be taken for the fastbus mode and
sync mode. In the fastbus mode, the BUS frequency in the CLKST[23:12] should be ignored and the CPU
frequency in the CLKST[11:0] should be taken for the BUS frequency because the CPU clock and system bus
clock is the same. In the sync mode, the BUS frequency in the CLKST[23:12] should also be ignored , and the
half of the CPU frequency should be taken for the BUS frequency.
Register Address
CLKST 0xF0000010
CLKST Bit
Clock Mode [31:30]
Reserved [29:24]
BUS Freq [23:12]
CPU Freq [11:0]

4.8.6 AHB BUS MASTER PRIORITY REGISTER

Register Address
HPRIF 0xF0000014
HPRIR 0xF0000018
R/W
R
00 = FastBus mode
10 = Reserved
01 = Synchronous
11 = Asynchronous
System Bus Clock frequency
CPU Clock frequency
R/W
R/W AHB bus master fixed priority register
R/W AHB bus master round-robin priority register
Description
Clock Status register (Read Only)
Description
Description
SYSTEM CONFIGURATION
Reset Value
–
Initial State
Reset Value
0x00543210
0x00000000
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