Section 21 Electrical Characteristics
21.3.4
Clock Timing
Clock timing is shown as follows:
• Oscillator settling timing
Figure 21.18 shows the oscillator settling timing.
φ
V
CC
STBY
t
OSC1
RES
21.3.5
TPC and I/O Port Timing
Figure 21.19 shows the TPC and I/O port timing.
φ
Port 1 to B
(read)
Port 1 to 6,
8 to B
(write)
Figure 21.19 TPC and I/O Port Input/Output Timing
Rev. 3.00 Mar 21, 2006 page 654 of 814
REJ09B0302-0300
Figure 21.18 Oscillator Settling Timing
T
T
1
2
t
PRS
T
3
t
PRH
t
PWD
t
OSC1