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25.3.1
Clock Timing
Table 25-5 lists the clock timing
Table 25-5 Clock Timing
Condition A: V
= PLLV
CC
V
= 3.6 V to AV
ref
T
= –20°C to +75°C (regular specifications), T
a
specifications)
Condition B: V
= PLLV
CC
V
= 4.5 V to AV
ref
T
= –20°C to +75°C (regular specifications), T
a
specifications)
Item
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
Clock oscillator settling
time at reset (crystal)
Clock oscillator settling
time in software standby
(crystal)
External clock output
stabilization delay time
32 kHz clock oscillation
settling time
Sub clock oscillator
frequency
Sub clock (ø
) cycle time t
SUB
Notes: *1 AV
= 3.3 V to 5.5 V if A/D and D/A not used (pins used as I/O ports).
CC
*2 Vref = 3.3 V to AV
= 3.0 V to 3.6 V, PV
CC
*
2
, V
= AV
CC
SS
SS
= 3.0 V to 3.6 V, PV
CC
, V
= AV
= PLLV
CC
SS
SS
Condition A
16MHz
Symbol
Min
Max
t
62.5
500
cyc
t
18
—
CH
t
18
—
CL
t
—
12
Cr
t
—
12
Cf
t
10
—
OSC1
t
8
—
OSC2
t
2
—
DEXT
t
—
2
OSC3
f
32.768
SUB
30.5
SUB
if A/D and D/A not used (pins used as I/O ports).
CC
= 3.0 V to 5.5 V, AV
CC
= PLLV
= 0 V, ø = 32.768 kHz, 2 to 16 MHz,
SS
= –40°C to +85°C (wide-range
a
= 4.5 V to 5.5 V, AV
CC
= 0 V, ø = 32.768 kHz, 2 to 25 MHz,
SS
= –40°C to +85°C (wide-range
a
Condition B
25MHz
Min
Max
40
500
15
—
15
—
—
5
—
5
20
—
10
—
2
—
—
2
32.768
30.5
= 3.6 V to 5.5 V *
CC
= 4.5 V to 5.5 V,
CC
Unit
Test Conditions
ns
Figure 25-2
ns
ns
ns
ns
ms
Figure 25-3
ms
Figure 24-3
ms
Figure 25-3
s
kHz
µs
1021
1
,
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