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To stop VBCLK oscillation by system reset when the NB85E901 is connected, input at least five VBCLK clocks
after the system reset has become low level to completely initialize the status of the pins related to the CPU and
the internal signals, then stop VBCLK oscillation. Unless this restriction is followed, the debugger may not start
successfully.
VBCLK (input)
DCRESZ (input)
Internal system
reset signal
(2) VBCLK (input)
This is the external clock input pin for the internal system clock. A 50% duty stable clock is input from an
external clock control circuit.
(3) CGREL (input)
This is the release input pin for the external clock generator (CG). An active level (high level) is input upon the
start of VBCLK input at least one clock after STOP mode is canceled and the oscillation stabilization time has
been ensured (it is not necessary to set CGREL input at the same time as VBCLK input).
(4) SWSTOPRQ (output)
This is the pin from which software STOP mode requests are output to the external clock generator (CG). When
software STOP mode is set, this pin outputs a high-level signal.
VBCLK input from the CG is stopped by using this signal. When software STOP mode is canceled, this pin
outputs a low-level signal.
(5) HWSTOPRQ (output)
This is the pin from which hardware STOP mode requests are output to the external clock generator (CG).
When hardware STOP mode is set by DCSTOPZ input, this pin outputs a high-level signal.
VBCLK input from the CG is stopped by using this signal. When hardware STOP mode is canceled, this pin
outputs a low-level signal.
(6) DCSTOPZ (input)
This is a hardware STOP mode request input pin. When a low-level signal is input, the NU85E is set to
hardware STOP mode.
(7) STPRQ (output)
This is the pin from which hardware/software STOP mode requests are output to the memory controller (MEMC).
(8) STPAK (input)
This is the pin to which acknowledge signals are input from the memory controller (MEMC) acknowledging the
STPRQ signal.
CHAPTER 2 PIN FUNCTIONS
Figure 2-2. Stopping VBCLK Oscillation by System Reset
At least 5 clocks
input during reset
Completion of initialization
Preliminary User's Manual A14874EJ3V0UM
VBCLK stopped after initialization
completed (except during power-on)
IC starts up 4 clocks
after reset release
Start of program execution
35
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