Figure 12.1 Block Diagram Of 8-Bit Timer Module - Renesas H8S/2368 Series Hardware Manual

Figure 12.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).
External clock source
TMCI0
TMCI1
TMO0
TMRI0
TMO1
TMRI1
A/D
conversion
start request
signal
Legend
TCORA_0 : Time constant register A_0
TCORB_0 : Time constant register B_0
TCNT_0 : Timer counter_0
TCSR_0 : Timer control/status register_0
TCR_0 : Timer control register_0
Rev. 2.00, 05/03, page 474 of 820
Internal clock sources
TMR_0
φ/8
φ/64
φ/8192
Clock 1
Clock select Clock 0
Compare match A1
Compare match A0
Overflow 1
Overflow 0
Compare match B1
Compare match B0
Control logic
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
Interrupt signals

Figure 12.1 Block Diagram of 8-Bit Timer Module

TMR_1
φ/8
φ/64
φ/8192
TCORA_0
Comparator A_0
TCNT_0
Clear 0
Clear 1
Comparator B_0
TCORB_0
TCSR_0
TCR_0
TCORA_1 : Time constant register A_1
TCORB_1 : Time constant register B_1
TCNT_1 : Timer counter_1
TCSR_1 : Timer control/status register_1
TCR_1 : Timer control register_1
TCORA_1
Comparator A_1
TCNT_1
Comparator B_1
TCORB_1
TCSR_1
TCR_1