Figure 13.2 Block Diagram Of Timer Connection - Renesas H8S/2437 Hardware Manual

Figure 13.2 shows a block diagram of the timer connection. The configuration of the timer
connection is the same in channels 0 and 1. However, the HFBACKI and VFBACKI inputs are
not available in channel 1.
Edge
detection
VSYNCI Phase
/ FTIA inversion
Edge
detection
Phase
VFBACKI
inversion
/ FTIB
FTIC
Phase
HSYNCI
inversion
/ TMI1
Edge
detection
Phase
CSYNCI
inversion
/ FTID
Edge
detection
Phase
HFBACKI
inversion
/ FTCI
Edge
detection
TMIX
READ
flag
IVI signal
IVI
signal
SET
selection
Sync
RES
FTIA
FRT
FTIB
input
selec-
FTIC
tion
FTID
TMR_Y
signal
selection
TMR_1
input
selection
IHI signal
IHI
TMR_X
signal
TMRI
input
selection
/TMCI
selection
CM1C
CLAMP waveform generator
READ
flag

Figure 13.2 Block Diagram of Timer Connection

VSYNC modify
16 bit FRT FTOA
SET
CMA(R)
OCRA +VR, +VF
RES VSYNC
ICRD +1M, +2M
CMA(F)
compare match generator
FTOB
CM1M CM2M
SET RES
2f H mask generator
2f H mask/ flag
CBLANK
waveform generator
TMRI/TMCI
8 bit TMR_Y IHG signal
TMO
CMB
TMCI
8 bit
TMO
TMR_1
TMRI
PDC signal
PWM decode
CMB
8 bit TMR_X
ICR
TMO
ICR +1C
compare match
CMA
CL1 signal
CL2 signal
CL3 signal
Rev. 1.00, 09/03, page 367 of 704
IVO
Phase
signal
inversion
selection
FRT
output
selection
VSYNCO
A
/ FTOA
IVG signal
IVO signal
FRT
output
selection
B
Phase
CBLANK
inversion
/FTOB
Phase
IHO
inversion
signal
TMO1
selection
output
selection
CL4 generator
CL4 signal
CLO
signal
Phase
selection
inversion
TMOY
HSYNCO
/ TMO1
TMOX
CLAMPO
/ FTIC