Table of Contents
Advertisement
Figure 10.20 Conflict between OCRAR/OCRAF Write and Compare-Match
10.7.4
Switching of Internal Clock and FRC Operation
When the internal clock is changed, the changeover may cause FRC to be incremented. This
depends on the timing at which the clock is switched (bits CKS1 and CKS0 are rewritten). Table
10.3 shows the relationship between the timing and the FRC operation.
When an internal clock is used, the FRC clock is generated on detection of the falling edge of the
internal clock scaled from the system clock (φ). If the clock is changed when the old source is high
and the new source is low, as in case no. 3 in table 10.3, the changeover is regarded as a falling
edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock
and external clock can also cause FRC to be incremented.
Rev. 1.00, 09/03, page 264 of 704
φ
Address
Internal write signal
OCRAR (OCRAF)
Compare-match signal
FRC
OCR
Automatic addition is not performed
because compare-match signals are disabled.
(When Automatic Addition Function is Used)
OCRAR (OCRAF)
address
Old data
New data
Disabled
N
N
N+1
Advertisement
Table of Contents
