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Settings and Operation (Examples when φ φ φ φ = 20 MHz)
Table 9.4
2
Resolution*
T
(µ µ µ µ s)
CFS
CKS
0
0.05
0
1
1
0.1
0
1
Notes: 1. Indicates the conversion cycle when specific bits in DADR are fixed.
2. Indicates the resolution when PWCKXC = PWCKXB = PWCKXA = 0.
Rev. 1.00, 09/03, page 234 of 704
Conver-sion
Base
Cycle
(µ µ µ µ s)
Cycle
TL/TH
(µ µ µ µ s)
(OS = 0/OS = 1)
3.2
819.2
Always low/high output
DA13 to DA0 = H'0000 to H'00FF
(Data value) × T
DA13 to DA0 = H'0100 to H'3FFF
12.8
819.2
Always low/high output
DA13 to DA0 = H'0000 to H'003F
(Data value) × T
DA13 to DA0 = H'0040 to H'3FFF
6.4
1638.4
Always low/high output
DA13 to DA0 = H'0000 to H'00FF
(Data value) × T
DA13 to DA0 = H'0100 to H'3FFF
25.6
1638.4
Always low/high output
DA13 to DA0 = H'0000 to H'003F
(Data value) × T
DA13 to DA0 = H'0040 to H'3FFF
Fixed DADR Bits
Conversion
Bit Data
Accuracy
(Bits)
14
12
0
10
0
0
0
14
12
0
10
0
0
0
14
12
0
10
0
0
0
14
12
0
10
0
0
0
Conversion
1
Cycle*
(µ µ µ µ s)
819.2
0
204.8
0
51.2
819.2
0
204.8
0
51.2
1638.4
0
409.6
0
102.4
1638.4
0
409.6
0
102.4
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