Valid Strobes; Figure 6.8 Access Sizes And Data Alignment Control (16-Bit Access Space); Table 6.3 Data Buses Used And Valid Strobes - Renesas H8S/2368 Series Hardware Manual

Byte size
Byte size
Word size
Longword
size

Figure 6.8 Access Sizes and Data Alignment Control (16-bit Access Space)

6.5.2

Valid Strobes

Table 6.3 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write,
the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Table 6.3 Data Buses Used and Valid Strobes
Access
Area Size
8-bit access Byte
space
16-bit access Byte
space
Word
Notes: Hi-Z: High-impedance state
Invalid: Input state; input value is ignored.
• Even address
• Odd address
1st bus cycle
2nd bus cycle
Read/
Write Address
Read —
Write —
Read Even
Odd
Write Even
Odd
Read —
Write —
Upper data bus
D15 D8 D7
Valid Upper Data Bus
Strobe (D15 to D8)
RD
Valid
HWR
RD
Valid
Invalid
HWR
Valid
LWR
Hi-Z
RD
Valid
HWR, LWR
Valid
Rev. 2.00, 05/03, page 139 of 820
Lower data bus
D0
Lower Data Bus
(D7 to D0)
Invalid
Hi-Z
Invalid
Valid
Hi-Z
Valid
Valid
Valid