Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1696

ADSP-SC58x MLB Register Descriptions
Interrupt Enable Register
The register is used to enable various interrupt conditions.
MLB_MIEN
ISOCBUFO (R/W)
Isochronous Receive Buffer Overflow
Enable
CTXBREAK (R/W)
Control Transmit Break Enable
CTXPE (R/W)
Control Transmit Protocol Error Enable
CTXDONE (R/W)
Control Transmit Packet Done Enable
CRXBREAK (R/W)
Control Receive Break Enable
CRXPE (R/W)
Control Receive Protocol Error Enable
CRXDONE (R/W)
Control Receive Packet Done Enable
ATXBREAK (R/W)
Asynchronous Transmit Break Enable
Figure 28-32: MLB_MIEN Register Diagram
Table 28-45: MLB_MIEN Register Fields
Bit No.
(Access)
29 CTXBREAK
(R/W)
28 CTXPE
(R/W)
27 CTXDONE
(R/W)
28–56
15 14 13 12 11 10 9
0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0
Bit Name
Control Transmit Break Enable.
When the MLB_MIEN.CTXBREAK bit is set, a ReceiverBreak response received from
the receiver on a control Tx channel causes the appropriate channel bit in the
MLB_MS0
Control Transmit Protocol Error Enable.
When the MLB_MIEN.CTXPE bit is set, a ProtocolError generated by the receiver on
a control Tx channel causes the appropriate channel bit in the
MLB_MS1
Control Transmit Packet Done Enable.
When the MLB_MIEN.CTXDONE bit is set, a packet transmitted with no errors on a
control Tx channel causes the appropriate channel bit in the
registers to be set.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
Description/Enumeration
or MLB_MS1 registers to be set.
registers to be set.
0
0
ISOCPE (R/W)
Isochronous Receive Protocol Error
Enable
0
SYNCPE (R/W)
Synchronous Protocol Error Enable
ARXDONE (R/W)
Asynchronous Receive Packet Done
Enable
ARXPE (R/W)
Asynchronous Receive Protocol Error
Enable
ARXBREAK (R/W)
Asynchronous Receive Break Enable
ATXDONE (R/W)
Asynchronous Transmit Done Enable
ATXPE (R/W)
Asynchronous Transmit Protocol Error
Enable
MLB_MS0
MLB_MS0
or
or MLB_MS1