Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1672

ADSP-SC58x MLB Register Descriptions
Peripheral Channel Status 1 Register
The register contains interrupt bits for each of the 64 physical channels. When a bit in this register is
MLB_ACSR1
set, it indicates that the corresponding physical channel has an interrupt pending.
A peripheral interrupt is triggered when either DNEn or ERRn is set within the Bus Channel Descriptor. The HC is
notified of the channel interrupt via MLB_INT[1:0]. When an interrupt occurs in ACCUSER (for channels 31 to
0) MLB_INT[0] is set. When an interrupt occurs in
Interrupts in the MLB_ACSR1
signal, MLB_INT[0], if the MLB_ACTL.SMX bit = 1.
If the MLB_ACTL.SCE bit =0, hardware automatically clears the interrupt bit(s) after the HC reads the peripheral
channel status registers. Alternatively, if the MLB_ACTL.SCE bit =1, software must write a 1 to the appropriate
bit(s) of peripheral channel status registers to clear the interrupt(s).
CHS[31:16] (R/W1C)
Channel Status
Figure 28-10: MLB_ACSR1 Register Diagram
Table 28-23: MLB_ACSR1 Register Fields
Bit No.
(Access)
31:0 CHS
(R/W1C)
28–32
and MLB_ACSR0
15
0
CHS[15:0] (R/W1C)
Channel Status
31
0
Bit Name
Channel Status.
The MLB_ACSR1.CHS bit field indicates channel status for channels 63-32.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
(for channels 63 to 32) MLB_INT[1] is set.
MLB_ACSR1
registers can be optionally multiplexed onto a single interrupt
14 13 12 11 10 9 8 7
0 0 0 0 0 0 0 0
30 29 28 27 26 25 24 23
0 0 0 0 0 0 0 0
Description/Enumeration
0 No interrupt on Channel 63:32 (bitwise; all channels
shown)
4294967295 Interrupt on Channel 63:32 (bitwise; all channels
shown)
6 5 4 3 2 1 0
0 0 0 0 0 0 0
22 21 20 19 18 17 16
0 0 0 0 0 0 0