Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1695

Memory Interface Control Data Write Enable 3 Register
The register contains the bitwise write enable for Channel Table RAM (CTR) data bits [127:96].
MLB_MDWE3
When cleared (=0), the bit is disabled. When set (=1), the bit is enabled.
Figure 28-31: MLB_MDWE3 Register Diagram
Table 28-44: MLB_MDWE3 Register Fields
Bit No.
(Access)
31:0 MSK
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15 14
0 0
MSK[15:0] (R/W)
Bitwise write enable for CTR data -
bits[127:96]
31 30
0 0
MSK[31:16] (R/W)
Bitwise write enable for CTR data -
bits[127:96]
Bit Name
Bitwise write enable for CTR data - bits[127:96].
The MLB_MDWE3.MSK bit field contains the bitwise write enable for CTR data.
13 12 11 10 9 8 7 6
0 0 0 0 0 0 0 0
29 28 27 26 25 24 23 22
0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x MLB Register Descriptions
5 4 3 2 1 0
0 0 0 0 0 0
21 20 19 18 17 16
0 0 0 0 0 0
28–55