Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1662

Operating Modes
the point it left off. In this situation, the PML is already known and the packet length is not reread or rewritten by
the HC.
During the reading of a packet, if the HC sets HCMD0.CMD[2:0]= 010 for the channel before the last byte of the
packet is read, an internal hardware pointer is reset to the beginning of the packet buffer. This situation requires that
the HC reread the PML (from HSTS1) and reread the packet data (from HDATn) from the beginning. In the same
manner, if the HC resets HCMD0.CMD[2:0]= 010 for the channel before the last byte of a packet is written, an
internal hardware pointer is reset to the beginning of the packet buffer. This situation requires that the HC rewrite
the PML (to HCMD1) and rewrite the packet data (to HDATn) from the beginning. Any previous packet data in
the buffer is overwritten.
Frame synchronization is not supported for asynchronous channels.
Synchronous Data Exchange
The MLB core provides two modes of operation; standard and multi-frame per sub-buffer which provide flexibility
for implementing synchronous channels. Channels configured for standard mode require less buffer space, but have
higher interrupt rates and more stringent latency requirements. Channels setup for multi-frame per sub-buffer mode
require more buffer space, but have lower interrupt rates and less stringent latency requirements.
To set up a channel in multi-frame per sub-buffer mode:
1. Program the MLB_CTL0.FCNT bit field to select the number of frames per sub-buffer.
2. Program the CAT to enable multi-frame sub-buffering (MFE= 1) for each particular channel.
3. Set the buffer depth in the CDT: BD= 4 × m × bpf 1 where: m = frames per sub-buffer, bpf = bytes per frame.
4. Repeat for additional synchronous channels
A sample synchronous data buffer is shown in the Synchronous Data Buffer Structure figure. Each data buffer con-
tains four sub-buffers and each sub-buffer contains space for 1 to 64 frames of data, determined by the
MLB_CTL0.FCNT bits.
Figure 28-6: Synchronous Data Buffer Structure
Data Transfer
Two modes of operation are supported for transferring channel data between the MLB and internal memory. DMA
allows the multi-channel DMA engine to manage data transfers without core intervention. Core driven mode (I/O
mode) allows software to manage the transfer of data between MLB and internal memory.
NOTE: All hardware channels must use the same data transfer method. Mixed mode operation where hardware
channels operate in both I/O mode and DMA mode is not supported.
28–22
BA
SYNCHRONOUS
SUB-BUFFER SUB-BUFFER
DATA BUFFER
0
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SUB-BUFFER SUB-BUFFER
1 2 3
BD