Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1679

HBI Channel Busy 0 Register
The HC can determine which channel(s) are busy by reading the
• it is currently loaded into one of the two AGUs
• the channel is enabled, CE = 1 from the Channel Allocation Table
• the DMA is active
When an HBI channel is busy, hardware may write back its local copy of the channel descriptor at any time. System
software should not write a CDT descriptor for a channel that is busy. Only two HBI channels can be busy at any
given time. Each bit of this register is read-only.
Figure 28-15: MLB_HCBR0 Register Diagram
Table 28-28: MLB_HCBR0 Register Fields
Bit No.
(Access)
31:0 CHB
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15 14 13
0 0 0
CHB[15:0] (R)
Channel Busy
31 30 29
0 0 0
CHB[31:16] (R)
Channel Busy
Bit Name
Channel Busy.
The MLB_HCBR0.CHB bit field contains the bitwise channel busy bit for channels
31:0. When a bit is cleared (=0) the channel is idle. When a bit is set (=1) the channel
is busy.
MLB_HCBR0
12 11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
28 27 26 25 24 23 22 21
0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x MLB Register Descriptions
register. An HBI channel is busy if:
4 3 2 1 0
0 0 0 0 0
20 19 18 17 16
0 0 0 0 0
28–39