Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1639

VBUS Control Register
The
USB_VBUS_CTL
Figure 27-117: USB_VBUS_CTL Register Diagram
Table 27-93: USB_VBUS_CTL Register Fields
Bit No.
(Access)
4 DRV
(R/NW)
3 DRVINT
(R/W1C)
2 DRVIEN
(R/W)
1 DRVOD
(R/W)
0 INVDRV
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
controls USB controller VBUS-related features.
7 6 5
0 0 0
DRV (R)
VBUS Drive
DRVINT (R/W1C)
VBUS Drive Interrupt
DRVIEN (R/W)
VBUS Drive Interrupt Enable
Bit Name
VBUS Drive.
The USB_VBUS_CTL.DRV bit indicates the state of the UTMI+ DrvVBUS signal
from the USB controller.
VBUS Drive Interrupt.
The USB_VBUS_CTL.DRVINT bit indicates the state of the DrvVBUSInt interrupt.
VBUS Drive Interrupt Enable.
The USB_VBUS_CTL.DRVIEN bit enables the DrvVBUS interrupt.
VBUS Drive Open Drain.
The USB_VBUS_CTL.DRVOD selects whether the DrvVBUS output is open drain.
VBUS Invert Drive.
The USB_VBUS_CTL.INVDRV bit selects whether the DrvVBUS output is invert-
ed.
4 3 2 1 0
0 0 0 0 0
INVDRV (R/W)
VBUS Invert Drive
DRVOD (R/W)
VBUS Drive Open Drain
Description/Enumeration
ADSP-SC58x USB Register Descriptions
27–227