Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1645

Table 28-1: ADSP-SC58x MLB Register List (Continued)
Name
MLB_MS0
MLB_MS1
MLB_MSD
MLB_MSS
MLB_PCTL0
ADSP-SC58x MLB Interrupt List
Table 28-2: ADSP-SC58x MLB Interrupt List
Interrupt Name
ID
162 MLB0_INT0
163 MLB0_INT1
164 MLB0_STAT
Media LB Protocol
The MediaLB topology supports communication among all MediaLB devices, including the MediaLB controller.
The bus interface consists of a uni-directional line for clock (MLBC), a bidirectional line for signal information
(MLBS), and a bidirectional line for data transfer (MLBD). The MediaLB topology supports one controller con-
nected to one or more devices, where the controller is the interface between the MediaLB devices and the MOST
network.
The MediaLB controller includes MediaLB device functionality, and also generates the MediaLB clock (MLBC) that
is synchronized to the MOST Network. This generated clock provides the timing for the entire MediaLB interface.
The MLBS line is a multiplexed signal which carries channel addresses generated by the MediaLB controller, as well
as command and RxStatus bytes from MediaLB devices. The MLBD line is driven by the transmitting MediaLB
device and is received by all other MediaLB devices, including the MediaLB controller. The MLBD line carries the
actual data (synchronous, asynchronous, control, or isochronous).
Once per MOST network frame, the MLB controller generates a unique frame sync pattern on the MLB_SIG line.
The end of the frame sync pattern defines the byte boundary and the channel boundary for the MLB_SIG and
MLB_DAT lines of all MLB devices.
The MLB controller manages the arbitration for all the channels on the MLB and grants bandwidth for all the MLB
devices. An MLB physical channel is defined as four bytes wide, or a quadlet. Physical channels can be grouped into
multiple quadlets (which do not have to be consecutive) to form an MLB logical channel, which is defined by a
unique channel address.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
Channel Status 0 Register
Channel Status 1 Register
System Data Register
System Status Register
MediaLB 6-pin Control 0 Register
Description
MLB0 Interrupt 0 channel 0-31
MLB0 Interrupt 1 channel 32-63
MLB0 Status
Functional Description
Sensitivity DMA
Channel
28–5