Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1657

Figure 28-4: Ping-Pong System Memory Structure
Each ADT entry (also referred to as a Channel Descriptor) holds a 32-bit BAn field which defines the start of each
ping or pong buffer within system memory. The BDn field is used to indicate the size for the respective ping or
pong page. The maximum size is 2k entries for asynchronous and control channels and 8k entries for isochronous
and synchronous channels.
Synchronous Channel Descriptors
The synchronous buffering scheme allows each ping or pong buffer to contain a single frame or a multiple number
of frames. For this reason, the synchronous buffer depth (BDn) must be defined in terms of an integer number (n),
frames per sub-buffer (m) and bytes per frame (bpf ) of data (for example BDn = n m bpf 1). The Synchronous ADT
Entry Format table shows the format for a synchronous ADT entry. The field definitions are defined in the ADT
Field Definitions table. Each synchronous channel buffer can be up to 8k-bytes deep.
Table 28-15: Synchronous ADT Entry Format
Bit Offset 15 14
0 CE
16
32 RDY1
48 RDY2
64
80
96
112
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
BA1
BA2
13 12
LE PG
DNE1 ERR1
DNE2 ERR2
4G - 1
PING BUFFER
(PG = 0)
PONG BUFFER
(PG = 1)
0
11 10 9 8 7
Reserved
BA1[15:0]
BA1[31:16]
BA2[15:0]
BA2[31:16]
BD1
BD2
6 5 4 3
Reserved
BD1[12:0]
BD2[12:0]
Channel Table RAM
2 1 0
28–17