Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1654

Channel Table RAM
Table 28-11: Isochronous CDT Entry Field Definitions (Continued)
Field
RSTS
WSTS
Reserved. Software writes a 0 to all these bits when the entry is initialized. Reserved bits are RO after initialization.
Asynchronous/Control Channel Descriptors
The format and field definitions for an Asynchronous/Control CDT entry are shown in the Asynchronous/Control
CDT Entry Format and Asynchronous/Control CDT Entry Field Definitions tables.
Table 28-12: Asynchronous/Control CDT Entry Format
Bit Offset 15
0
16
32 Rsvd
48 Rsvd
64
80
96 RSTS[4] WSTS[4
112 Rsvd
Table 28-13: Asynchronous/Control CDT Entry Field Definitions
Field
BA
BD
28–14
Description
Read Status
Write Status
14 13 12
WPC[4:0]
RPC[4:0]
WPC[7:5]
RPC[7:5]
WSTS[3:0]
RSTS[3:0]
Rsvd
]
Description
Buffer Base Address
Buffer Depth
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Details
Software initializes to 0, hardware updates.
RSTS States:
xx1 = active
xx0 = idle
Software initializes to 0, hardware updates.
WSTS States:
xxx0 =active
xxx1 = idle
xx0x = command protocol error
1xxx = buffer overflow (FCE = 0 only)
11 10 9 8
Details
Can start at any byte in the 16k DBR.
BD = size of buffer in bytes 1.
Buffer end address = BA + BD.
BD = max packet length 1.
7 6 5 4 3
Reserved
Reserved
Reserved
Reserved
WPTR[11:0]
RPTR[11:0]
BD[11:0]
BA[13:0]
Access
RWU
RWU
RWU
2 1 0
Access
RW
RW