Section 2 CPU
2.7.1
Instructions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can
use.
Table 2.2
Combinations of Instructions and Addressing Modes (1)
Classifi-
cation
Instruction
Data transfer
MOV
MOVFPE,
MOVTPE*
POP, PUSH
LDM, STM
MOVA*
Block
EEPMOV
transfer
MOVMD
MOVSD
Arithmetic
ADD, CMP
operations
SUB
ADDX, SUBX
INC, DEC
ADDS, SUBS
DAA, DAS
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Size
#xx
Rn
B/W/L
S
SD
B
S/D
B
S/D
12
W/L
S/D
L
S/D
4
B/W
S
B
B/W/L
B
B
S
D
B
S
B
D
B
W/L
S
SD
B
S
B
S
B
D
B
W/L
S
SD
B/W/L
S
SD
B/W/L
S
B/W/L
S
B/W/L
D
L
D
B
D
Addressing Mode
@(d,
RnL.B/
Rn.W/
@ERn
@(d,ERn)
ERn.L)
SD
SD
SD
S
S
S
D
D
D
D
D
D
S
S
S
SD
SD
SD
SD
SD
SD
D
D
D
D
D
D
S
S
S
SD
SD
SD
SD
SD
SD
SD
@−ERn/
@ERn+/
@ERn−/
@aa:16/
@+ERn
@aa:8
@aa:32
SD
SD
S/D
1
S/D*
2
S/D*
2
S/D*
S
S
D
D
D
D
D
D
S
S
S
SD
SD
SD
SD
D
D
D
D
D
D
S
S
S
SD
SD
SD
SD
5
SD*
3
SD*
3
SD*
3
SD*