Instruction Formats; Cpu Instruction Addressing Modes; Table 2.11 Addressing Modes And Effective Addresses For Cpu Instructions - Renesas HD6417641 Hardware Manual

Section 2 CPU
2.4

Instruction Formats

2.4.1

CPU Instruction Addressing Modes

The following table shows addressing modes and effective address calculation methods for
instructions executed by the CPU core.

Table 2.11 Addressing Modes and Effective Addresses for CPU Instructions

Addressing Instruction
Mode Format
Register direct Rn
Register indirect @Rn
Register @Rn+
indirect with
post-increment
Register @–Rn
indirect with
pre-decrement
Rev. 4.00 Sep. 14, 2005 Page 48 of 982
REJ09B0023-0400
Effective Address Calculation Method
Effective address is register Rn.
(Operand is register Rn contents.)
Effective address is register Rn contents.
Rn
Effective address is register Rn contents.
A constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn
Rn + 1/2/4
+
1/2/4
Effective address is register Rn contents. It is
decremented by a constant beforehand: 1 for
a byte operand, 2 for a word operand, 4 for
a longword operand.
Rn
Rn – 1/2/4
–
1/2/4
Calculation Formula

Rn
Rn
Rn
After instruction execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Rn
Longword: Rn + 4 → Rn
Byte: Rn – 1 → Rn
Word: Rn – 2 → Rn
Longword: Rn – 4 → Rn
(Instruction executed with Rn
after calculation)
Rn – 1/2/4