Table of Contents
Advertisement
2.6.2
Instructions and Addressing Modes
Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU
can use.
Table 2-2
Combinations of Instructions and Addressing Modes
Function
Instruction
MOV
Data
transfer
POP, PUSH
LDM, STM
MOVFPE,
MOVTPE *
1
ADD, CMP
Arithmetic
operations
SUB
ADDX, SUBX
ADDS, SUBS
INC, DEC
DAA, DAS
MULXU,
DIVXU
MULXS,
DIVXS
NEG
EXTU, EXTS
TAS *
2
AND, OR,
Logic
operations
XOR
NOT
Shift
Bit manipulation
Branch
Bcc, BSR
JMP, JSR
RTS
System
TRAPA
control
RTE
SLEEP
LDC
STC
ANDC,
ORC, XORC
NOP
Block data transfer
Legend:
Size refers to the operand size.
B: Byte
W: Word
L: Longword
Notes: 1. Cannot be used in the H8S/2319 and H8S/2318 Groups.
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 5.00, 12/03, page 40 of 1088
BWL
BWL
BWL
BWL
BWL
BWL
WL
BWL
B
B
L
BWL
B
BW
BW
BWL
WL
B
BWL
BWL
BWL
BWL
B
B
B
B
W
W
B
W
W
B
Addressing Modes
BWL
BWL
B
BWL
B
B
B
W
W
W
W
W
W
BWL
B
W
W
WL
L
BW
Advertisement
Table of Contents
