Extension Of Chip Select (Cs) Assertion Period; Figure 6.18 Example Of Read Strobe Timing - Renesas H8S/2368 Series Hardware Manual

Address bus
RDNn = 0
Data bus
RDNn = 1
Data bus
6.5.6 Extension of Chip Select (CS
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert
states in which only the CS, AS, and address signals are asserted before and after a basic bus space
access cycle. Extension of the CS assertion period can be set for individual areas. With the CS
assertion extension period in write access, the data setup and hold times are less stringent since the
write data is output to the data bus.
Figure 6.19 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.
Rev. 2.00, 05/03, page 150 of 820
T
1

Figure 6.18 Example of Read Strobe Timing

CS) Assertion Period CS CS
Bus cycle
T
2
T
3