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12.5
Operating Description
12.5.1
Endian/Access Size and Data Alignment
This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the
byte data.
Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and byte-
selection SRAM. Two data bus width (16 bits and 32 bits) are available for SDRAM. Data bus
width for MPX-IO is fixed to 32 bits. Data alignment is performed in accordance with the data bus
width of the device. This also means that when longword data is read from a byte-width device,
the read operation must be done four times. In this LSI, data alignment and conversion of data
length is performed automatically between the respective interfaces.
Table 12.5 through 12.7 show the relationship between device data width and access unit.
Table 12.5 32-Bit External Device Access and Data Alignment
D31 to
Operation
D24
Byte access
Data
at 0
7 to 0
Byte access
at 1
Byte access
at 2
Byte access
at 3
Word access
Data
at 0
15 to 8
Word access
at 2
Longword
Data
access at 0
31 to 24
Data Bus
D23 to
D15 to
D16
D8
D7 to D0
Data
7 to 0
Data
7 to 0
Data
7 to 0
Data
15 to 8
Data
Data
23 to 16
15 to 8
Section 12 Bus State Controller (BSC)
WE3,
WE2,
DQMUU
DQMUL
Assert
Data
7 to 0
Assert
Data
7 to 0
Data
Assert
7 to 0
Rev. 4.00 Sep. 14, 2005 Page 321 of 982
Strobe Signals
WE1,
WE0,
DQMLU
DQMLL
Assert
Assert
Assert
Assert
Assert
Assert
REJ09B0023-0400
Assert
Assert
Assert
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