Cs Assertion Period Control Registers H, L (Csacrh, Csacrl) - Renesas H8S/2368 Series Hardware Manual

CS Assertion Period Control Registers H, L (CSACRH, CSACRL)

CS
CS CS
6.3.5
CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip
select signals (CSn) and address signals is to be extended. Extending the assertion period of the
CSn and address signals allows flexible interfacing to external I/O devices.
• CSACRH
Bit Bit Name
7 CSXH7
6 CSXH6
5 CSXH5
4 CSXH4
3 CSXH3
2 CSXH2
1 CSXH1
0 CSXH0
• CSACRL
Bit Bit Name
7 CSXT7
6 CSXT6
5 CSXT5
4 CSXT4
3 CSXT3
2 CSXT2
1 CSXT1
0 CSXT0
Rev. 2.00, 05/03, page 118 of 820
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
CS and Address Signal Assertion Period
Control 1
These bits specify whether or not the T
to be inserted (see figure 6.3). When an area for
which the CSXHn bit is set to 1 is accessed, a
cycle, in which only the CSn and
one-state T
h
address signals are asserted, is inserted before
the normal access cycle.
0: In area n basic bus interface access, the CSn
and address assertion period (T
extended
1: In area n basic bus interface access, the CSn
and address assertion period (T
Description
CS and Address Signal Assertion Period
Control 2
These bits specify whether or not the T
shown in figure 6.3 is to be inserted. When an
area for which the CSXTn bit is set to 1 is
accessed, a one-state T
CSn and address signals are asserted, is
inserted before the normal access cycle.
0: In area n basic bus interface access, the CSn
and address assertion period (T
extended
1: In area n basic bus interface access, the CSn
and address assertion period (T
cycle is
h
) is not
h
) is extended
h
(n = 7 to 0)
cycle
t
cycle, in which only the
t
) is not
t
) is extended
t
(n = 7 to 0)