Block Diagram - Samsung S3C2501X User Manual

PRODUCT OVERVIEW

1.3 BLOCK DIAGRAM

Ethernet
Ethernet
2-bank
SDRAM
8-bank
Flash/ROM/
SRAM/Ext
I/O
REQ/ACK
External
Bus Master
1-4
10/100
DMA
MAC
10/100
DMA
MAC
133
MHz
AHB
BUS
Memory
Controller
Figure 1-1. S3C2501X Block Diagram
4KB
D-Cache
A
H
ARM940T
B
(166 MHz)
I/F
4KB
D-Cache
Interrupt
Controller
APB
Bridge
DES/3DES
Sys. Bus
Arbiter
WDT
Six
GDMA
Six
Timers
Clock Gen.
&
Reset Drv. with 4
PLLs
20 MHz or
10 MHz
25 MHz
OSC.
S3C2501X
High
Speed
UART
Console
UART
2
I C
133
MHz
APB
BUS
GPIOs