External Clock Source - Samsung S5PV210 Hardware Design Manual

S5PV210_HARDWARE DESING GUIDE REV 1.0

27.2. External Clock Source

To make PCM Serial clock and PCM Frame Sync, PCM interface controller divides EPLL, MPLL or PCLK When
these clocks are divided, its advantage is that it is not necessary to configure oscillator circuit(for feeding auxiliary
clock(256fs/384fs) to Codec chip (MCLK), please refer to SEC).
If an oscillator circuit is configured for a precise clock for the Sampling Frequency without PLLs or Internal clocks,
there is a way to accept to this frequency as source of PCM Serial clock and PCM Frame Sync through the
XpcmEXTCLK line.
27.3. Connection Example
This example shows PCM connection using WM8580 Secondary interface. For Primary interface refer I2S multi audio
interface.
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