Timer Interrupt Enable Registers (Tier) - Renesas H8S/2319 series Hardware Manual

9.2.4

Timer Interrupt Enable Registers (TIER)

Channel 0: TIER0
Channel 3: TIER3
Bit : 7
TTGE
Initial value : 0
R/W : R/W
Channel 1: TIER1
Channel 2: TIER2
Channel 4: TIER4
Channel 5: TIER5
Bit : 7
TTGE
Initial value : 0
R/W : R/W
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has six TIER registers, one for each channel. The TIER registers are
initialized to H'40 by a reset and in hardware standby mode.
Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D
conversion start requests by TGRA input capture/compare match.
Bit 7
TTGE Description
0 A/D conversion start request generation disabled
1 A/D conversion start request generation enabled
Bit 6—Reserved: This bit cannot be modified and is always read as 1.
Rev. 5.00, 12/03, page 324 of 1088
6 5
— — TCIEV
1 0
— — R/W
6 5
— TCIEU TCIEV
1 0
— R/W R/W
4 3 2
TGIED TGIEC
0 0 0
R/W R/W
4 3 2
— —
0 0 0
— —
1 0
TGIEB TGIEA
0 0
R/W R/W
1 0
TGIEB TGIEA
0 0
R/W R/W
(Initial value)