Location Of Register Information And Dtc Vector Table; Figure 8.2 Block Diagram Of Dtc Activation Source Control; Table 8.1 Relationship Between Activation Sources And Dtcer Clearing - Renesas H8S/2368 Series Hardware Manual

Table 8.1 Relationship between Activation Sources and DTCER Clearing
Activation Source
Activation by software
Activation by an interrupt
Source flag cleared
On-chip
supporting
module
IRQ interrupt
DTVECR

Figure 8.2 Block Diagram of DTC Activation Source Control

8.4

Location of Register Information and DTC Vector Table

Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF).
Register information should be located at the address that is multiple of four within the range.
Locating the register information in address space is shown in figure 8.3. Locate the MRA, SAR,
MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register
information. In the case of chain transfer, register information should be located in consecutive
areas as shown in figure 8.3 and the register information start address should be located at the
corresponding vector address to the activation source. Figure 8.4 shows the correspondence
between the DTC vector address and register information. The DTC reads the start address of the
DISEL = 0 and Specified
Number of Transfers Has
Not Ended
SWDTE bit is cleared to 0
•
Corresponding DTCER bit
remains set to 1.
•
Activation source flag is
cleared to 0.
Clear
DTCER
Select
Interrupt
request
DISEL = 1 or Specified Number
of Transfers Has Ended
•
SWDTE bit remains set to 1
•
Interrupt request to CPU
•
Corresponding DTCER bit is
cleared to 0.
•
Activation source flag remains
set to 1.
•
Interrupt that became the
activation source is requested
to the CPU.
Clear
controller
Clear request
DTC
Interrupt controller
Interrupt mask
Rev. 2.00, 05/03, page 281 of 820
CPU