Exception Sources And Exception Vector Table - Renesas H8S/2100 Series Hardware Manual

Section 4 Exception Handling
4.2

Exception Sources and Exception Vector Table

Different vector addresses are assigned to exception sources. Table 4.2 and table 4.3 list the
exception sources and their vector addresses. The EIVS bit in the system control register 3
(SYSCR3) allows the selection of the H8S/2140B Group compatible vector mode or extended
vector mode.
Table 4.2 Exception Handling Vector Table
(H8S/2140B Group Compatible Vector Mode)
Exception Source
Reset
Reserved for system use
Illegal instruction
Reserved for system use
Direct transition
External interrupt (NMI)
Trap instruction (four sources)
Reserved for system use
External interrupt IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6,
KIN7 to KIN0
IRQ7,
KIN15 to KIN8
Rev. 1.00 Apr. 28, 2008 Page 76 of 994
REJ09B0452-0100
Vector Addresses
Vector
Number Advanced Mode
0 H'000000 to H'000003
1 H'000004 to H'000007

3 H'00000C to H'00000F
4 H'000010 to H'000013
5 H'000014 to H'000017
6 H'000018 to H'00001B
7 H'00001C to H'00001F
8 H'000020 to H'000023
9 H'000024 to H'000027
10 H'000028 to H'00002B
11 H'00002C to H'00002F
12 H'000030 to H'000033

15 H'00003C to H'00003F
16 H'000040 to H'000043
17 H'000044 to H'000047
18 H'000048 to H'00004B
19 H'00004C to H'00004F
20 H'000050 to H'000053
21 H'000054 to H'000057
22 H'000058 to H'00005B
23 H'00005C to H'00005F
|
|