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9FGV100x Register Descriptions and Programming Guide User Guide
Appendix 1: Fractional Output Divider Configuration
The Fractional Output Divider (FOD) is composed of an 8 bit integer portion (address 0x12) and a 16 bit fractional portion (addresses
0x13 and 0x14).
FOD value P = INT(P) + FRAC(P) = F
/ (2 × F
) (1)
VCO
OUT
FOD Integer [7..0] = DEC2HEX(INT(P)) (2)
The FOD divides the VCO frequency F
down to the desired output frequency F
. Please note the additional /2 between the VCO
VCO
OUT
and the FOD.
Convert FRAC(P) to hex with Eq.2 where ROUND2INT means to round to the nearest integer. The round-off error of P in ppm is the
output frequency error in ppm.
16
FOD Fraction [15..0] = DEC2HEX(ROUND2INT(2
×FRAC(P))) (3)
Example: If the VCO is 2500MHz and the desired output frequency is 148.5MHz, the FOD value is 2500/(2×148.5)=8.4175084.
The integer portion is 8 so address 0x12 will be 08-hex.
The fractional portion is 0.4175084.
16
FOD Fraction [15..0] = DEC2HEX(ROUND2INT(2
×0.4175084) = DEC2HEX(ROUND2INT(27361.83))
= DEC2HEX(27362) = 6A E2
Address 0x13 = 6A-hex and address 0x14 = E2-hex.
16
There is a small error from the rounding. The actual FOD value is 8 + 27362 / 2
= 8.4175110.
The rounding error is 8.4175110 / 8.4175084 - 1 = 0.31ppm.
©2016 Integrated Device Technology, Inc.
10
November 18, 2016
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