Output Terminations And Rework To Take 1Pps Input; Schematic Diagrams - Renesas RC32012A Manual

RC32012A Evaluation Kit Manual
2.3

Output Terminations and Rework to Take 1PPS Input

All outputs are terminated by a 100-ohm resistor across the output pair. This is the recommended termination
regardless of the Voffset and Vswing settings. Since the outputs are DC-coupled, they will support a 1PPS output
without any need for rework.
Note: When connecting the outputs to measurement equipment, use a DC-block to ensure that the output
operates at its intended Voffset; otherwise, the equipment may load the output down and cause degraded
performance.
The following rework must be implemented in order to support a 1PPS input clock. All input clocks for the
evaluation board are AC-coupled and terminated as in Figure 15.
Figure 15. Input Clock's AC-coupling and Terminations
For a 1PPS input, a single-ended input with DC-coupling is recommended. As such, the populated AC-coupling
capacitor must be removed and the input must be configured as LVCMOS, not differential. In Figure 15, to make
CLK0 supportive of 1PPS input, first configure CLK0 as LVCMOS in Timing Commander (see Figure 16).
Figure 16. Configuring CLK0 as CMOS to Receive a 1PPS Input
Once in LVCMOS mode, CLK0_P and CLK0_N will be two separate LVCMOS inputs instead of a differential pair.
To make CLK0_P receive a 1PPS input, replace C881 with a 0-ohm resistor, while at the same time, remove R765
and R770.
3.

Schematic Diagrams

Schematic diagrams are located at the rear of the document.
R31UH0010EU0102 Rev.1.02 Page 14
Apr 20, 2022