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Texas Instruments TMS570LS Manuals
Manuals and User Guides for Texas Instruments TMS570LS. We have
1
Texas Instruments TMS570LS manual available for free PDF download: Getting Started
Texas Instruments TMS570LS Getting Started (39 pages)
AEC-Automotive
Brand:
Texas Instruments
| Category:
Microcontrollers
| Size: 1 MB
Table of Contents
Table of Contents
1
1 Block Diagram
3
Figure 1. Device Block Diagram
3
2 Overview of Features
4
3 Standard Initialization Sequence for TMS570LS Microcontrollers
7
Enabling Floating Point Coprocessor (FPU)
8
Initialization of Cortex-R4F Registers
9
Initialize Stack Pointers for All CPU Operating Modes
11
Enable the Cortex-R4F Cpu"S Vectored Interrupt Controller (VIC) Port
12
Configure Flash Access
13
Figure 2. Flash Read Control Register: FRDCNTL, Address = 0Xfff87000
13
Configure Flash Bank and Pump Power Modes
14
Figure 3. Flash Bank Fall-Back Control Register: FBFALLBACK, Address = 0Xfff87040
14
Figure 4. Flash Bank Access Control Register: FBAC, Address = 0Xfff8703C
15
Figure 5. Flash Pump Access Control Register 1: FPAC1, Address = 0Xfff87048
16
Figure 6. Flash Pump Access Control Register 2: FPAC2, Address = 0Xfff8704C
16
Configure Plls
17
Fmzpll
17
Figure 7. Fmzpll Block Diagram
17
Figure 8. PLL Control Register 1: PLLCTL1, Address = 0Xffffff70
18
Figure 9. PLL Control Register 2: PLLCTL2, Address = 0Xffffff74
19
Fpll
20
Figure 10. FPLL Block Diagram
20
Figure 11. PLL Control Register 3: PLLCTL3, Address = 0Xffffe100
21
Enable Clock Sources
22
Available Clock Sources on TMS570LS Microcontrollers
22
Table 1. Clock Sources on TMS570LS Microcontrollers
22
Control Registers for Enabling and Disabling Clock Sources
23
Figure 12. Clock Source Disable Register: CSDIS, Address = 0Xffffff30
23
Figure 13. Clock Source Disable Set Register: CSDISSET, Address = 0Xffffff34
23
Example Clock Source Configuration
24
Figure 14. Clock Source Disable Clear Register: CSDISCLR, Address = 0Xffffff38
24
Clock Domains
25
Table 2. Clock Domains on TMS570LS Microcontrollers
25
Figure 15. GCLK, HCLK , Vclkx Source Register: GHVSRC, Address = 0Xffffff48
26
Figure 16. Asynchronous Clock Source Register: VCLKASRC, Address = 0Xffffff4C
26
Mapping Clock Domains to Clock Sources
26
Configuring VCLK and VCLK2 Frequencies
27
Example Clock Domain Mapping
27
Figure 17. RTI Clock Source Register: RCLKSRC, Address = 0Xffffff50
27
Figure 18. Peripheral Clock Control Register: CLKCNTL, Address = 0Xffffffd0
28
Run CPU Self-Test
29
Release Reset and Clocks to Peripherals
30
Memories" Self-Test
31
Memories" Auto-Initialization
32
Figure 19. Memory Hardware Initialization Global Control Register: MINITGCR, Address = 0Xffffff5C
32
Figure 21. Memory Self-Test / Initialization Status Register: MSTCGSTAT, Address
33
Vectored Interrupt Manager Configuration
34
Example VIM RAM Configuration
34
Figure 22. VIM Interrupt Address Memory Map
34
Configure Interrupts to be Fast Interrupts or Normal Interrupts
36
Enabling Interrupts
36
Figure 23. FIQ/IRQ Control Register 0: FIRQPR0, Address = 0Xfffffe10
36
Figure 24. FIQ/IRQ Control Register 1: FIRQPR1, Address = 0Xfffffe14
36
Figure 25. Interrupt Enable Set Register 0: REQENASET0, Address = 0Xfffffe30
37
Figure 26. Interrupt Enable Set Register 1: REQENASET1, Address = 0Xfffffe34
37
Figure 27. Interrupt Enable Clear Register 0: REQENACLR0, Address = 0Xfffffe40
37
Figure 28. Interrupt Enable Clear Register 1: REQENACLR1, Address = 0Xfffffe44
38
Additional Initializations Required by Compiler
39
Call the Main Application
39
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