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Texas Instruments RM48 series Manuals
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Texas Instruments RM48 series manual available for free PDF download: Technical Reference Manual
Texas Instruments RM48 series Technical Reference Manual (1759 pages)
16/32-Bit RISC Flash Microcontroller
Brand:
Texas Instruments
| Category:
Microcontrollers
| Size: 11 MB
Table of Contents
Rm48X 16/32-Bit Risc Flash Microcontroller Technical Reference Manual
2
Table of Contents
2
18
28
Ram Memory Map/Flash Bank Busy Register (Fbbusy) [Offset = 38H]
34
Table of Contents
45
Table of Contents
50
76
Preface
87
1 Introduction
89
Designed for Safety Applications
90
Family Description
90
Endianism Considerations
93
Rm48X: Little Endian (LE)
93
2 Architecture
94
Introduction
95
Architecture Block Diagram
95
Definitions of Terms
96
Bus Master / Slave Access Privileges
98
Memory Organization
99
Memory-Map Overview
99
Memory-Map Table
100
Flash Memory
104
On-Chip SRAM
106
Exceptions
111
Aborts
111
Resets
111
System Software Interrupts
113
Clocks
114
Clock Sources
114
Clock Domains
115
Low Power Modes
117
Clock Test Mode
119
Embedded Trace Macrocell (ETM-R4)
120
Safety Considerations for Clocks
121
System and Peripheral Control Registers
123
Primary System Control Registers (SYS)
123
Secondary System Control Registers (SYS2)
176
Peripheral Central Resource (PCR) Control Registers
185
3 Power Management Module (PMM)
200
Overview
201
Block Diagram
201
Main Features of the Power Management Module (PMM)
201
Power Domains
202
PMM Operation
204
Changing Power Domain State
204
Default Power Domain State
204
Disabling a Power Domain Permanently
204
Power Domain State
204
Power Switch
204
Diagnostic Power State Controller (PSCON)
205
PSCON Compare Block
205
Reset Management
205
SPNU503C - March 2018
227
Flash Uncorrectable Error Address Register (FUNC_ERR_ADD) [Offset = 20H]
274
Flash Error Detection and Correction Sector Disable Register (FEDACSDIS) [Offset = 24H]
275
Primary Address Tag Register (FPRIM_ADD_TAG) [Offset = 28H]
276
Duplicate Address Tag Register (FDUP_ADD_TAG) [Offset = 2Ch]
276
Flash Bank Protection Register (FBPROT) [Offset = 30H]
277
Flash Bank Sector Enable Register (FBSE) [Offset = 34H]
277
Flash Bank Busy Register (FBBUSY) [Offset = 38H]
278
Flash Bank Access Control Register (FBAC) [Offset = 3Ch]
279
Flash Bank Fallback Power Register (FBFALLBACK) [Offset = 40H]
280
Flash Bank/Pump Ready Register (FBPRDY) [Offset = 44H]
281
Flash Pump Access Control Register 1 (FPAC1) [Offset = 48H]
282
Flash Pump Access Control Register 2 (FPAC2) [Offset = 4Ch]
283
Flash Module Access Control Register (FMAC) [Offset = 50H]
283
Flash Module Status Register (FMSTAT) [Offset = 54H]
284
EEPROM Emulation Data MSW Register (FEMU_DMSW) [Offset = 58H]
286
EEPROM Emulation Data LSW Register (FEMU_DLSW) [Offset = 5Ch]
286
EEPROM Emulation ECC Register (FEMU_ECC) [Offset = 60H]
287
EEPROM Emulation Address Register (FEMU_ADDR) [Offset = 68H]
288
Diagnostic Control Register (FDIAGCTRL) [Offset = 6Ch]
289
Uncorrected Raw Data High Register (FRAW_DATAH) [Offset = 70H]
291
Uncorrected Raw Data Low Register (FRAW_DATAL) [Offset = 74H]
291
Uncorrected Raw ECC Register (FRAW_ECC) [Offset = 78H]
292
Parity Override Register (FPAR_OVR) [Offset = 7Ch]
293
Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2) [Offset = C0H]
294
FSM Register Write Enable (FSM_WR_ENA) [Offset = 288H]
295
FSM Sector Register (FSM_SECTOR) [Offset = 2A4H]
295
EEPROM Emulation Configuration Register (EEPROM_CONFIG) [Offset = 2B8H]
296
EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1) [Offset = 308H]
297
EEPROM Emulation Error Correction and Correction Control Register 2 (EE_CTRL2) [Offset = 30Ch]
299
EEPROM Emulation Error Correctable Error Count Register (EE_COR_ERR_CNT) [Offset = 310H]
299
EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD) [Offset = 314H]
300
EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS) [Offset = 318H]
301
EEPROM Emulation Error Status Register (EE_STATUS) [Offset = 31Ch]
302
EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD) [Offset = 320H]
303
Flash Bank Configuration Register (FCFG_BANK) [Offset = 400H]
304
TCRAM Module Connections
306
RAM Memory Map
307
TCRAM Module Control Register (RAMCTRL) [Offset = 00H]
311
TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD) [Offset = 04H]
312
TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR) [Offset = 08H]
313
TCRAM Module Interrupt Control Register (RAMINTCTRL) [Offset = 0Ch]
313
TCRAM Module Error Status Register (RAMERRSTATUS) [Offset = 10H]
314
TCRAM Module Single-Bit Error Address Register (RAMSERRADDR) [Offset = 14H]
315
TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR) [Offset = 1Ch]
316
TCRAM Module Test Mode Control Register (RAMTEST) [Offset = 30H]
317
TCRAM Module Test Mode Vector Register (RAMADDRDECVECT) [Offset = 38H]
318
TCRAM Module Parity Error Address Register (RAMPERRADDR) [Offset = 3Ch]
318
Auto-Memory Initialization Enable Register (INIT_DOMAIN) [Offset = 40H]
319
PBIST Block Diagram
321
PBIST Memory Self-Test Flow Diagram
323
RAM Configuration Register (RAMT) [Offset = 0160H]
328
Datalogger Register (DLR) [Offset = 0164H]
329
PBIST Activate/Rom Clock Enable Register (PACT) [Offset = 0180H]
330
PBIST ID Register [Offset = 184H]
331
Override Register (OVER) [Offset = 0188H]
332
Fail Status Fail Register 0 (FSRF0) [Offset = 0190H]
333
Fail Status Count 0 Register (FSRC0) [Offset = 0198H]
334
Fail Status Count Register 1 (FSRC1) [Offset = 019Ch]
334
Fail Status Address 0 Register (FSRA0) [Offset = 01A0H]
335
Fail Status Address 1 Register (FSRA1) [Offset = 01A4H]
335
Fail Status Data Register 0 (FSRDL0) [Offset = 01A8H]
336
Fail Status Data Register 1 (FSRDL1) [Offset = 01B0H]
336
ROM Mask Register (ROM) [Offset = 01C0H]
337
ROM Algorithm Mask Register (ALGO) [Offset = 01C4H]
337
RAM Info Mask Lower Register (RINFOL) [Offset = 01C8H]
338
RAM Info Mask Upper Register (RINFOU) [Offset = 01Cch]
339
STC Block Diagram
344
Application Self-Test Flow Chart
346
STC Global Control Register 0 (STCGCR0) [Offset = 00]
349
STC Global Control Register 1 (STCGCR1) [Offset = 04H]
349
Self-Test Run Timeout Counter Preload Register (STCTPR) [Offset = 08H]
350
STC Current ROM Address Register (STC_CADDR) [Offset = 0Ch]
350
STC Current Interval Count Register (STCCICR) [Offset = 10H]
351
Self-Test Global Status Register (STCGSTAT) [Offset = 14H]
352
Self-Test Fail Status Register (STCFSTAT) [Offset = 18H]
353
CPU1 Current MISR Register (CPU1_CURMISR3) [Offset = 1Ch]
354
CPU1 Current MISR Register (CPU1_CURMISR2) [Offset = 20H]
354
CPU1 Current MISR Register (CPU1_CURMISR1) [Offset = 24H]
354
CPU1 Current MISR Register (CPU1_CURMISR0) [Offset = 28H]
354
CPU2 Current MISR Register (CPU2_CURMISR3) [Offset = 2Ch]
355
CPU2 Current MISR Register (CPU2_CURMISR2) [Offset = 30H]
355
CPU2 Current MISR Register (CPU2_CURMISR1) [Offset = 34H]
355
CPU2 Current MISR Register (CPU2_CURMISR0) [Offset = 38H]
355
Signature Compare Self-Check Register (STCSCSCR) [Offset = 3Ch]
356
Block Diagram
359
CCM-R4F Status Register (CCMSR) (Address = FFFF F600H)
364
CCM-R4F Key Register (CCMKEYR) (Address = FFFF F604H)
365
Clock Path from Oscillator through PLL to Device
368
Clock Generation Path
369
Oscillator Implementation
370
Operation of the FM-PLL Module
374
PLL Slip Detection and Reset/Bypass Block Diagram
380
SSW PLL bist Control Register 1 (SSWPLL1) [Offset = Ff24H]
385
SSW PLL bist Control Register 2 (SSWPLL2) [Offset = Ff28H]
386
SSW PLL bist Control Register 3 (SSWPLL3) [Offset = Ff2Ch]
387
Basic PLL Circuit
388
PFD Timing
388
PLL Modulation Block Diagram
389
Frequency Vs. Time
390
DCC Operation
393
Counter Relationship
395
Clock1 Slower than Clock0 - Results in an Error and Stops Counting
395
Clock1 Faster than Clock0 - Results in an Error and Stops Counting
396
Clock1 Not Present - Results in an Error and Stops Counting
396
Clock0 Not Present - Results in an Error and Stops Counting
397
DCC Global Control Register (DCCGCTRL) [Offset = 00]
400
DCC Revision ID Register (DCCREV) [Offset = 4H]
401
DCC Counter0 Seed Register (DCCCNT0SEED) [Offset = 8H]
401
DCC Valid0 Seed Register (DCCVALID0SEED) [Offset = Ch]
402
DCC Counter1 Seed Register (DCCCNT1SEED) [Offset = 10H]
402
DCC Status Register (DCCSTAT) [Offset = 14H]
403
DCC Counter0 Value Register (DCCCNT0) [Offset = 18H]
404
DCC Valid0 Value Register (DCCVALID0) [Offset = 1Ch]
405
DCC Counter1 Value Register (DCCCNT1) [Offset = 20H]
405
DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) [Offset = 24H]
406
DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) [Offset = 28H]
407
Block Diagram
409
Interrupt Response Handling
410
ERROR Pin Response Handling
410
ERROR Pin Timing - Example 1
412
ERROR Pin Timing - Example 2
412
ERROR Pin Timing - Example 3
412
ERROR Pin Timing - Example 4
413
ERROR Pin Timing - Example 5
413
ERROR Pin Timing - Example 7
414
ESM Initialization
415
ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1) [Address = FFFF F500H]
417
ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1) [Address = FFFF F504H]
417
ESM Interrupt Enable Set Register 1 (ESMIESR1) [Address = FFFF F508H]
418
ESM Interrupt Enable Clear Register 1 (ESMIECR1) [Address = FFFF F50Ch]
418
ESM Interrupt Level Set Register 1 (ESMILSR1) [Address = FFFF F510H]
419
ESM Interrupt Level Clear Register 1 (ESMILCR1) [Address = FFFF F514H]
419
ESM Status Register 1 (ESMSR1) [Address = FFFF F518H]
420
ESM Status Register 2 (ESMSR2) [Address = FFFF F51Ch]
420
ESM Status Register 3 (ESMSR3) [Address = FFFF F520H]
421
ESM ERROR Pin Status Register (ESMEPSR) [Address = FFFF F524H]
421
ESM Interrupt Offset High Register (ESMIOFFHR) [Address = FFFF F528H]
422
ESM Interrupt Offset Low Register (ESMIOFFLR) [Address = FFFF F52Ch]
423
ESM Low-Time Counter Register (ESMLTCR) [Address = FFFF F530H]
424
ESM Low-Time Counter Preload Register (ESMLTCPR) [Address = FFFF F534H]
424
ESM Error Key Register (ESMEKR) [Address = FFFF F538H]
425
ESM Status Shadow Register 2 (ESMSSR2) [Address = FFFF F53Ch]
425
ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4) [Address = FFFF F540H]
426
ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4) [Address = FFFF F544H]
426
ESM Interrupt Enable Set Register 4 (ESMIESR4) [Address = FFFF F548H]
427
ESM Interrupt Enable Clear Register 4 (ESMIECR4) [Address = FFFF F54Ch]
427
ESM Interrupt Level Set Register 4 (ESMILSR4) [Address = FFFF F550H]
428
ESM Interrupt Level Clear Register 4 (ESMILCR4) [Address = FFFF F554H]
428
ESM Status Register 4 (ESMSR4) [Address = FFFF F558H]
429
RTI Block Diagram
432
Counter Block Diagram
433
Compare Unit Block Diagram (Shows Only 1 of 4 Blocks for Simplification)
435
Timebase Control
436
Clock Detection Scheme
436
Switch to Ntux
437
Missing Ntux Signal Example
438
Digital Watchdog
438
DWD Operation
439
Digital Windowed Watchdog Timing Example
440
Digital Windowed Watchdog Operation Example (25% Window)
440
RTI Global Control Register (RTIGCTRL) [Offset = 00]
443
RTI Timebase Control Register (RTITBCTRL) [Offset = 04H]
444
RTI Capture Control Register (RTICAPCTRL) [Offset = 08H]
445
RTI Compare Control Register (RTICOMPCTRL) [Offset = 0Ch]
446
RTI Free Running Counter 0 Register (RTIFRC0) [Offset = 10H]
447
RTI up Counter 0 Register (RTIUC0) [Offset = 14H]
447
RTI Compare up Counter 0 Register (RTICPUC0) [Offset = 18H]
448
RTI Capture Free Running Counter 0 Register (RTICAFRC0) [Offset = 20H]
448
RTI Capture up Counter 0 Register (RTICAUC0) [Offset = 24H]
449
RTI Free Running Counter 1 Register (RTIFRC1) [Offset = 30H]
449
RTI up Counter 1 Register (RTIUC1) [Offset = 34H]
450
RTI Compare up Counter 1 Register (RTICPUC1) [Offset = 38H]
451
RTI Capture Free Running Counter 1 Register (RTICAFRC1) [Offset = 40H]
452
RTI Capture up Counter 1 Register (RTICAUC1) [Offset = 44H]
452
RTI Compare 0 Register (RTICOMP0) [Offset = 50H]
453
RTI Update Compare 0 Register (RTIUDCP0) [Offset = 54H]
453
RTI Compare 1 Register (RTICOMP1) [Offset = 58H]
454
RTI Update Compare 1 Register (RTIUDCP1) [Offset = 5Ch]
454
RTI Compare 2 Register (RTICOMP2) [Offset = 60H]
455
RTI Update Compare 2 Register (RTIUDCP2) [Offset = 64H]
455
RTI Compare 3 Register (RTICOMP3) [Offset = 68H]
456
RTI Update Compare 3 Register (RTIUDCP3) [Offset = 6Ch]
456
RTI Timebase Low Compare Register (RTITBLCOMP) [Offset = 70H]
457
RTI Timebase High Compare Register (RTITBHCOMP) [Offset = 74H]
457
RTI Set Interrupt Control Register (RTISETINTENA) [Offset = 80H]
458
RTI Clear Interrupt Control Register (RTICLEARINTENA) [Offset = 84H]
460
RTI Interrupt Flag Register (RTIINTFLAG) [Offset = 88H]
462
Digital Watchdog Control Register (RTIDWDCTRL) [Offset = 90H]
463
Digital Watchdog Preload Register (RTIDWDPRLD) [Offset = 94H]
464
Watchdog Status Register (RTIWDSTATUS) [Offset = 98H]
465
RTI Watchdog Key Register (RTIDWDKEY) [Offset = 9Ch]
466
RTI Watchdog down Counter Register (RTIDWDCNTR) [Offset = A0H]
467
Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) [Offset = A4H]
467
Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) [Offset = A8H]
468
RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) [Offset = Ach]
469
RTI Compare 0 Clear Register (RTICMP0CLR) [Offset = B0H]
470
Loop Resolution Instruction Execution Example
806
HR I/O Architecture
807
Example of HR Structure Sharing for N2HET Pins 0/1
808
XOR-Shared HR I/O
809
Symmetrical PWM with XOR-Sharing Output
810
AND-Shared HR I/O
810
HR0 to HR1 Digital Loopback Logic: LBTYPE[0] = 0
811
HR0 to HR1 Analog Loop Back Logic: LBTYPE[0] = 1
812
N2HET Input Edge Detection
813
ECMP Execution Timings
814
High/Low Resolution Modes for ECMP and PWCNT
815
PCNT Instruction Timing (with Capture Edge after HR Counter Overflow)
816
PCNT Instruction Timing (with Capture Edge before HR Counter Overflow)
816
WCAP Instruction Timing
817
I/O Block Diagram Including Pull Control Logic
818
N2HET Pin Disable Feature Diagram
819
Suppression Filter Counter Operation
821
Interrupt Functionality on Instruction Level
822
Interrupt Flag/Priority Level Architecture
823
Request Line Assignment Example
824
Operation of N2HET Count Instructions
825
SCNT Count Operation
825
ACNT Period Variation Compensations
826
N2HET Timings Associated with the Gap Flag (ACNT Deceleration)
827
N2HET Timings Associated with the Gap Flag (ACNT Acceleration)
828
Angle Generator Principle
829
Hardware Angle Generator Block Diagram
830
Angle Tick Generation Principle
831
New Angle Tick Generation Architecture
832
Angle Generation Using Time Based Algorithm
833
SCNT Stepping Compensation
833
ACNT During Acceleration and Deceleration
834
Singularity Check, ACNT Reset and Timing Associated
835
Example of HWAG Start Sequence
836
Code
837
Gap Verification Criteria for a 60-2 Toothed Wheel
838
Using the ARST Bit in a Toothed Wheel Without Singularity
839
Windowing Filter for Toothed Wheel Input on Falling Active Edge
840
Filtering During Singularity Tooth
841
HWAG Interrupt Block Diagram
842
Hardware Angle Generator/High End Timer Interface
844
Angle Count Within the HWAG at Resolution Clock
844
Angle Count Within the NHET with Increments
845
Compare Without ACMP Instruction
845
Example of ACMP Compare Within the NHET
846
NHET Interface Block Diagram
847
Global Configuration Register (HETGCR) [Offset = 00H]
852
Prescale Factor Register (HETPFR)
854
N2HET Current Address (HETADDR)
855
HWAG Filter Register 2 (HWAFIL2) Field Descriptions
892
HWAG Angle Increment Register (HWAANGI) Field Descriptions
893
Instruction Summary
894
FLAGS Generated by Instruction
895
Interrupt Capable Instructions
895
Arithmetic / Bitwise Logic Sub-Opcodes
907
Source Operand Choices
907
Destination Operand Choices
907
Shift Encoding
908
Execution Time for ADC, ADD, AND, OR, SBB, SUB, XOR Instructions
908
Move Types for ADM32
913
Edge Select Encoding for APCNT
916
Branch Condition Encoding for BR
919
DADM64 Control Field Description
924
Event Encoding Format for ECNT
932
Magnitude Compare Order for MCMP
934
Move Type Encoding Selection
937
MOV64 Control Field Descriptions
941
Comparison Type Encoding Format
942
Counter Type Encoding Format
944
Comparison Type Encoding Format
951
RADM64 Control Field Descriptions
951
Step Width Encoding for SCNT
957
SHIFT MODE Encoding Format
959
SHIFT Condition Encoding
959
Event Encoding Format for WCAP
962
Event Encoding Format for WCAPE
964
CPENA / Tmbx Priority Rules
973
Triggered Control Packets
976
Dcp Ram
978
DCP Parity RAM
978
Field Addresses of the WCAP, ECNT, PCNT Example
979
32-Bit-Transfer of Data Fields
980
Destination Buffer Values
980
64-Bit-Transfer of Control Field and Data Fields
981
Destination Buffer Values
981
HTU Control Registers
982
Global Control Register (HTU GC) Field Descriptions
983
Control Packet Enable Register (HTU CPENA) Field Descriptions
984
CPENA Write Results
984
CPENA Read Results
984
Control Packet (CP) Busy Register 0 (HTU BUSY0) Field Descriptions
985
Control Packet (CP) Busy Register 1 (HTU BUSY1) Field Descriptions
986
Control Packet (CP) Busy Register 2 (HTU BUSY2) Field Descriptions
986
Control Packet (CP) Busy Register 3 (HTU BUSY3) Field Descriptions
987
Active Control Packet and Error Register (HTU ACPE) Field Descriptions
987
Request Lost and Bus Error Control Register (HTU RLBECTRL) Field Descriptions
989
Buffer Full Interrupt Enable Set Register (HTU BFINTS) Field Descriptions
990
Buffer Full Interrupt Enable Clear Register (HTU BFINTC) Field Descriptions
990
GIO Block Diagram
1022
Device Modes of Operation
1024
Emulation Mode
1024
Power-Down Mode (Low-Power Mode)
1024
GIO Control Registers
1025
GIO Global Control Register (GIOGCR0)
1026
GIO Interrupt Detect Register (GIOINTDET)
1027
GIO Interrupt Polarity Register (GIOPOL)
1028
GIO Interrupt Enable Registers (GIOENASET and GIOENACLR)
1029
GIO Interrupt Priority Registers (GIOLVLSET and GIOLVLCLR)
1031
GIO Interrupt Flag Register (GIOFLG)
1034
GIO Offset Register 1 (GIOOFF1)
1035
GIO Offset B Register (GIOOFF2)
1036
GIO Emulation a Register (GIOEMU1)
1037
GIO Emulation B Register (GIOEMU2)
1038
GIO Emulation 2 Register (GIOEMU2) [Offset = 30H]
1038
GIO Data Direction Registers (GIODIR[A-B])
1039
GIO Data Input Registers (GIODIN[A-B])
1039
GIO Data Direction Registers (GIODIR[A-B]) [Offset = 34H, 54H]
1039
GIO Data Input Registers (GIODIN[A-B]) [Offset = 38H, 58H]
1039
GIO Data Output Registers (GIODOUT[A-B])
1040
GIO Data Set Registers (GIODSET[A-B])
1040
GIO Data Output Registers (GIODOUT[A-B]) [Offset = 3Ch, 5Ch]
1040
GIO Data Set Registers (GIODSET[A-B]) [Offset = 40H, 60H]
1040
GIO Data Clear Registers (GIODCLR[A-B])
1041
GIO Open Drain Registers (GIOPDR[A-B])
1041
GIO Data Clear Registers (GIODCLR[A-B]) [Offset = 44H, 64H]
1041
GIO Open Drain Registers (GIOPDR[A-B]) [Offset = 48H, 68H]
1041
GIO Pull Disable Registers (GIOPULDIS[A-B])
1042
GIO Pull Select Registers (GIOPSL[A-B])
1042
GIO Pull Disable Registers (GIOPULDIS[A-B]) [Offset = 4Ch, 6Ch]
1042
GIO Pull Select Registers (GIOPSL[A-B]) [Offset = 50H, 70H]
1042
I/O Control Summary
1043
Controller Area Network (DCAN) Module
1044
Features
1045
Functional Description
1045
Overview
1045
CAN Blocks
1046
CAN Core
1046
Message Handler
1046
Message RAM
1046
Block Diagram
1046
Dual Clock Source
1047
Message RAM Interface
1047
Register and Message Object Access
1047
Bit Time and Bit Rate
1048
CAN Bit Timing
1048
Bit Timing
1048
DCAN Bit Timing Registers
1050
CAN Module Configuration
1052
CAN Module Initialization
1052
DCAN RAM Initialization through Hardware
1052
CAN Bit-Timing Configuration
1052
Message RAM
1054
Structure of a Message Object
1054
Addressing Message Objects in RAM
1056
Message RAM Representation in Debug/Suspend Mode
1057
Message RAM Representation in RAM Direct Access Mode
1057
Message Interface Register Sets
1058
Data Transfer between IF1 / IF2 Registers and Message RAM
1059
Configuration of a Single Receive Object for Data Frames
1061
Configuration of a Transmit Object for Data Frames
1061
Configuration of a Transmit Object for Remote Frames
1061
Message Object Configurations
1061
Initialization of a Transmit Object
1061
Initialization of a Single Receive Object for Data Frames
1061
Configuration of a FIFO Buffer
1062
Configuration of a Single Receive Object for Remote Frames
1062
Reconfiguration of Message Objects for the Reception of Frames
1062
Reconfiguration of Message Objects for the Transmission of Frames
1062
Initialization of a Single Receive Object for Remote Frames
1062
Message Handler Overview
1063
Message Handling
1063
Receive/Transmit Priority
1063
Changing a Transmit Object
1064
Transmission of Messages in Event Driven CAN Communication
1064
Updating a Transmit Object
1064
Acceptance Filtering of Received Messages
1065
Reading Received Messages
1065
Reception of Data Frames
1065
Reception of Remote Frames
1065
Reading from a FIFO Buffer
1066
Requesting New Data for a Receive Object
1066
Storing Received Messages in FIFO Buffers
1066
CPU Handling of a FIFO Buffer (Interrupt Driven)
1067
Automatic Retransmission
1068
CAN Message Transfer
1068
Interrupt Functionality
1069
Message Object Interrupts
1069
Error Interrupts
1070
Status Change Interrupts
1070
CAN Interrupt Topology 1
1070
Entering Global Power-Down Mode
1071
Global Power-Down Mode
1071
CAN Interrupt Topology 2
1071
Entering Local Power-Down Mode
1072
Local Power-Down Mode
1072
GIO Support
1073
Local Power-Down Mode Flow Diagram
1073
Silent Mode
1074
Test Modes
1074
CAN Core in Silent Mode
1074
Loop Back Mode
1075
CAN Core in Loop Back Mode
1075
External Loop Back Mode
1076
CAN Core in External Loop Back Mode
1076
Loop Back Combined with Silent Mode
1077
CAN Core in Loop Back Combined with Silent Mode
1077
Behavior on Parity Error
1078
Parity Check Mechanism
1078
Parity Testing
1078
Debug/Suspend Mode
1079
CAN Control Register (DCAN CTL)
1081
CAN Control Register (DCAN CTL) [Offset = 00]
1081
Error and Status Register (DCAN ES)
1083
Error and Status Register (DCAN ES) [Offset = 04H]
1083
Error Counter Register (DCAN ERRC)
1085
Error Counter Register (DCAN ERRC) [Offset = 08H]
1085
Bit Timing Register (DCAN BTR)
1086
Bit Timing Register (DCAN BTR) [Offset = 0Ch]
1086
Interrupt Register (DCAN INT)
1087
Interrupt Register (DCAN INT) [Offset = 10H]
1087
Test Register (DCAN TEST)
1088
Test Register (DCAN TEST) [Offset = 14H]
1088
Core Release Register (DCAN REL)
1089
Parity Error Code Register (DCAN PERR)
1089
Parity Error Code Register (DCAN PERR) [Offset = 1Ch]
1089
Core Release Register (DCAN REL) [Offset = 20H]
1089
Auto-Bus-On Time Register (DCAN ABOTR)
1090
Transmission Request X Register (DCAN TXRQ X)
1090
Auto-Bus-On Time Register (DCAN ABOTR) [Offset = 80H]
1090
Transmission Request X Register (DCAN TXRQ X) [Offset = 84H]
1090
Transmission Request Registers (DCAN TXRQ12 to DCAN TXRQ78)
1091
Transmission Request 12 Register [Offset = 88H]
1091
Transmission Request 34 Register [Offset = 8Ch]
1091
Transmission Request 56 Register [Offset = 90H]
1091
Transmission Request 78 Register [Offset = 94H]
1091
New Data X Register (DCAN NWDAT X)
1092
New Data X Register (DCAN NWDAT X) [Offset = 98H]
1092
New Data Registers (DCAN NWDAT12 to DCAN NWDAT78)
1093
New Data 12 Register [Offset = 9Ch]
1093
New Data 34 Register [Offset = A0H]
1093
New Data 56 Register [Offset = A4H]
1093
New Data 78 Register [Offset = A8H]
1093
Interrupt Pending X Register (DCAN INTPND X)
1094
Interrupt Pending X Register (DCAN INTPND X) [Offset = Ach]
1094
Interrupt Pending 12 Register [Offset = B0H]
1095
Interrupt Pending 34 Register [Offset = B4H]
1095
Interrupt Pending Registers (DCAN INTPND12 to DCAN INTPND78)
1095
Message Valid X Register (DCAN MSGVAL X)
1096
Message Valid Registers (DCAN MSGVAL12 to DCAN MSGVAL78)
1097
Interrupt Multiplexer Registers (DCAN INTMUX12 to DCAN INTMUX78)
1098
IF1/IF2 Command Registers (DCAN IF1CMD, DCAN IF2CMD)
1099
IF1/IF2 Mask Registers (DCAN IF1MSK, DCAN IF2MSK)
1102
IF1/IF2 Arbitration Registers (DCAN IF1ARB, DCAN IF2ARB)
1103
IF1/IF2 Message Control Registers (DCAN IF1MCTL, DCAN IF2MCTL)
1104
IF1/IF2 Data a and Data B Registers (DCAN IF1DATA/DATB, DCAN IF2DATA/DATB)
1106
IF3 Observation Register (DCAN IF3OBS)
1107
IF3 Mask Register (DCAN IF3MSK)
1109
IF3 Arbitration Register (DCAN IF3ARB)
1110
IF3 Message Control Register (DCAN IF3MCTL)
1111
IF3 Data a and Data B Registers (DCAN IF3DATA/DATB)
1112
IF3 Update Enable Registers (DCAN IF3UPD12 to IF3UPD78)
1113
CAN TX IO Control Register (DCAN TIOC)
1114
CAN RX IO Control Register (DCAN RIOC)
1115
Multi-Buffering (Mib) Support
1118
Word Format Options
1118
Operating Modes
1119
Transmission Lock (Multi-Buffer Mode Master Only)
1119
Data Handling
1120
Pin Configurations
1120
Operation with SPICS
1123
Operation with SPIENA
1124
Five-Pin Operation (Hardware Handshaking)
1125
Data Formats
1126
Clocking Modes
1127
Data Transfer Example
1129
Decoded and Encoded Chip Select (Master Only)
1130
Hold Chip-Select Active
1130
Variable Chip Select Setup and Hold Timing (Master Only)
1130
Detection of Slave Desynchronization (Master Only)
1131
Data-Length Error
1132
ENA Signal Time-Out (Master Only)
1132
Parallel Mode (Multiple SIMO/SOMI Support, Not Available on All Devices)
1134
Continuous Self-Test (Master/Slave)
1140
Half Duplex Mode
1140
Internal Loop-Back Test Mode (Master Only)
1140
Test Features
1140
Input/Output Loopback Test Mode
1141
General-Purpose I/O
1142
Low-Power Mode
1142
Interrupts in Multi-Buffer Mode
1143
DMA in Multi-Buffer Mode
1145
DMA Interface
1145
Multi-Buffer RAM Receive Buffer Register (RXRAM)
1219
Parity Memory
1221
Example of Parity Memory Organization
1223
Master Mode Timings for Spi/Mibspi
1224
Mibspi Pin Timing Parameters
1224
Slave Mode Timings for Spi/Mibspi
1226
Master Mode Timing Parameter Details
1227
Slave Mode Timing Parameter Details
1227
Serial Communication Interface (SCI)/ Local Interconnect Network (LIN) Module
1228
Introduction and Features
1229
SCI Features
1229
LIN Features
1230
SCI Communication Formats
1234
SCI Frame Formats
1234
SCI Baud Rate
1235
SCI Timing Mode
1235
SCI Multiprocessor Communication Modes
1238
SCI Multi-Buffered Mode
1240
SCI Interrupts
1242
Receive Interrupt
1243
Transmit Interrupt
1243
Wakeup Interrupt
1243
Error Interrupts
1244
Receive DMA Requests
1245
SCI DMA Interface
1245
Transmit DMA Requests
1245
Receiving Data
1246
SCI Configurations
1246
Transmitting Data
1247
SCI Low-Power Mode
1248
Sleep Mode for Multiprocessor Communication
1248
LIN Communication Formats
1249
LIN Standards
1249
Baud Rate
1252
Synchronizer
1252
Header Generation
1254
Extended Frames Handling
1258
Timeout Control
1259
TXRX Error Detector (TED)
1260
Message Filtering and Validation
1263
Receive Buffers
1265
Transmit Buffers
1266
LIN DMA Interface
1267
LIN Interrupts
1267
LIN Receive DMA Requests
1267
LIN Transmit DMA Requests
1267
Receiving Data
1268
Transmitting Data
1269
Entering Sleep Mode
1270
Non-Isochronous, Non-Setup out (USB HOST→CPU) Transactions
1593
Non-Isochronous in (CPU→USB HOST) Transactions
1597
Isochronous out (USB HOST→CPU) Transactions
1600
Isochronous in (CPU→USB HOST) Transactions
1602
USB Device Initialization
1611
Preparing for Transfers
1614
Important Note on USB Device Interrupts
1617
Parsing General USB Device Interrupt
1617
USB Device Interrupt Service Routine (ISR) Flowcharts
1617
Setup Interrupt Handler
1618
Endpoint 0 RX Interrupt Handler
1621
Endpoint 0 TX Interrupt Handler
1622
Device States Changed Handler
1625
Device States Attached/Unattached Handler
1628
Device State Configuration Changed Handler
1629
Device State Address Changed Handler
1630
USB Device Reset Interrupt Handler
1630
Suspend/Resume Interrupt Handler
1631
Parsing Non-ISO Endpoint-Specific Interrupt
1632
Non-ISO, Non-Control out Endpoint Receive Interrupt Handler
1633
Non-ISO, Non-Control in Endpoint Transmit Interrupt Handler
1636
SOF Interrupt Handler
1638
Summary of USB Device Controller Interrupts
1641
DMA Operation
1642
Power Management
1651
USB Connectivity
1654
Selecting and Configuring USB Connectivity
1654
Transceiver Interface
1654
Transceiver Signaling
1655
Host Controller Connectivity with USB Transceivers
1656
USB Function Controller Connectivity with USB Transceivers
1657
USB Hardware Considerations
1658
Data Modification Module (DMM)
1659
Block Diagram
1660
Features
1660
Module Operation
1661
Data Format
1661
Data Port
1663
Error Handling
1664
Interrupts
1665
Copyright © 2018, Texas Instruments Incorporated
1759
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