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Texas Instruments SimpleLink MSP432E4 Technical Reference Manual

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MSP432E4 SimpleLink™ Microcontrollers

Technical Reference Manual

Literature Number: SLAU723A

October 2017 – Revised October 2018

Table of Contents

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Page 1 MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual Literature Number: SLAU723A October 2017 – Revised October 2018...
Page 2 Introduction ....................Functional Description ..................2.2.1 System Timer (SysTick) ..............2.2.2 Nested Vectored Interrupt Controller (NVIC) ................... 2.2.3 System Control Block (SCB) Contents SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 3 Shift Registers ..................3.3.4 Operational Considerations ..................Initialization and Configuration ..................... Register Descriptions ..................3.5.1 Instruction Register (IR) ....................3.5.2 Data Registers SLAU723A – October 2017 – Revised October 2018 Contents Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 4 4.2.42 PPWD Register (Offset = 0x300) [reset = 0x3] ............4.2.43 PPTIMER Register (Offset = 0x304) [reset = 0xFF] ............ 4.2.44 PPGPIO Register (Offset = 0x308) [reset = 0x3FFFF] Contents SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 5 4.2.95 RCGCEPHY Register (Offset = 0x630) [reset = 0x0] ............4.2.96 RCGCCAN Register (Offset = 0x634) [reset = 0x0] ............4.2.97 RCGCADC Register (Offset = 0x638) [reset = 0x0] SLAU723A – October 2017 – Revised October 2018 Contents Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 6 4.2.148 PCWD Register (Offset = 0x900) [reset = 0x3] ............4.2.149 PCTIMER Register (Offset = 0x904) [reset = 0xFF] ........... 4.2.150 PCGPIO Register (Offset = 0x908) [reset = 0x3FFFF] Contents SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 7 SYSEXCMIS Register (Offset = 0x8) [reset = 0x0] ............5.2.4 SYSEXCIC Register (Offset = 0xC) [reset = 0x0] ......................Hibernation Module ........................ Introduction ......................Block Diagram ....................Functional Description SLAU723A – October 2017 – Revised October 2018 Contents Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 8 ............6.5.27 HIBCC Register (Offset = 0xFC8) [reset = 0x0] ........................ Internal Memory ......................Block Diagram ....................Functional Description ......................7.2.1 SRAM Contents SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 9 ....................Functional Description ......................8.3.1 Priority ....................8.3.2 Arbitration Size ....................8.3.3 Request Types ..................8.3.4 Channel Configuration ....................8.3.5 Transfer Modes SLAU723A – October 2017 – Revised October 2018 Contents Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 10 9.2.1 AES Block Diagram ....................9.2.2 AES Algorithm ..................9.2.3 AES Operating Modes ..................... 9.2.4 AES Software Reset ..................... 9.2.5 Power Management Contents SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 11 10.5.13 ADCDCISC Register (Offset = 0x34) [reset = 0x0] ............10.5.14 ADCCTL Register (Offset = 0x38) [reset = 0x0] ............ 10.5.15 ADCSSMUX0 Register (Offset = 0x40) [reset = 0x0] SLAU723A – October 2017 – Revised October 2018 Contents Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 12 11.4.5 CANINT Register (Offset = 0x10) [reset = 0x0] .............. 11.4.6 CANTST Register (Offset = 0x14) [reset = X] ............11.4.7 CANBRPE Register (Offset = 0x18) [reset = X] Contents SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 13 DES Module Programming Guide – Low Level Programming Models ..............14.6.1 Surrounding Modules Global Initialization ................14.6.2 Operational Modes Configuration ..................14.6.3 DES Events Servicing ......................14.7 DES Registers SLAU723A – October 2017 – Revised October 2018 Contents Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 14 15.6.8 EMACVLANTG Register (Offset = 0x1C) [reset = 0x0] ............ 15.6.9 EMACSTATUS Register (Offset = 0x24) [reset = 0x0] ............ 15.6.10 EMACRWUFF Register (Offset = 0x28) [reset = 0x0] Contents SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 15 ..........15.6.62 EMACMFBOC Register (Offset = 0xC20) [reset = 0x0] 1031 ..........15.6.63 EMACRXINTWDT Register (Offset = 0xC24) [reset = 0x0] 1032 SLAU723A – October 2017 – Revised October 2018 Contents Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 16 1091 ....................16.4.2 SDRAM Mode 1091 ....................16.4.3 Host Bus Mode 1095 ..................16.4.4 General-Purpose Mode 1115 ......................16.5 EPI Registers 1122 Contents SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 17 ............17.5.4 GPIOIBE Register (Offset = 0x408) [reset = 0x0] 1207 ............17.5.5 GPIOIEV Register (Offset = 0x40C) [reset = 0x0] 1208 SLAU723A – October 2017 – Revised October 2018 Contents Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 18 1267 ..................18.4 Initialization and Configuration 1268 ................ 18.4.1 One-Shot and Periodic Timer Mode 1268 ................18.4.2 Real-Time Clock (RTC) Mode 1268 Contents SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 19 ............19.5.6 I2CMRIS Register (Offset = 0x14) [reset = 0x0] 1347 ............19.5.7 I2CMMIS Register (Offset = 0x18) [reset = 0x0] 1349 SLAU723A – October 2017 – Revised October 2018 Contents Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 20 ..........20.7.11 LCDRASTRTIM0 Register (Offset = 0x2C) [reset = 0x0] 1412 ..........20.7.12 LCDRASTRTIM1 Register (Offset = 0x30) [reset = 0x0] 1413 Contents SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 21 21.5.21 PWMnGENB Register [reset = 0x0] 1482 ..............21.5.22 PWMnDBCTL Register [reset = 0x0] 1484 ..............21.5.23 PWMnDBRISE Register [reset = 0x0] 1485 SLAU723A – October 2017 – Revised October 2018 Contents Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 22 .............. 23.5.3 SSIDR Register (Offset = 0x8) [reset = 0x0] 1543 .............. 23.5.4 SSISR Register (Offset = 0xC) [reset = 0x3] 1544 Contents SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 23 25.2.5 SHA_DATA_n_IN Registers (Offset = 0x080 to 0x0BC) [reset = 0x0] 1608 ........25.2.6 SHA_REVISION Register (Offset = 0x100) [reset = 0x40000C03] 1609 SLAU723A – October 2017 – Revised October 2018 Contents Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 24 ..........26.5.26 UARTPeriphID3 Register (Offset = 0xFEC) [reset = 0x1] 1667 ..........26.5.27 UARTPCellID0 Register (Offset = 0xFF0) [reset = 0xD] 1668 Contents SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 25 ............ 27.5.34 USBCSRL0 Register (Offset = 0x102) [reset = 0x0] 1737 ........... 27.5.35 USBCSRH0 Register (Offset = 0x103) [reset = 0x0] 1740 SLAU723A – October 2017 – Revised October 2018 Contents Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 26 ..........28.5.1 WDTLOAD Register (Offset = 0x0) [reset = 0xFFFFFFFF] 1802 ..........28.5.2 WDTVALUE Register (Offset = 0x4) [reset = 0xFFFFFFFF] 1802 Contents SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 27 28.5.19 WDTPCellID2 Register (Offset = 0xFF8) [reset = 0x6] 1815 ..........28.5.20 WDTPCellID3 Register (Offset = 0xFFC) [reset = 0xB1] 1815 ........................Revision History 1816 SLAU723A – October 2017 – Revised October 2018 Contents Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 28: Table Of Contents
....................... 2-26. MMADDR Register ....................2-27. FAULTADDR Register ...................... 2-28. MPUTYPE Register ...................... 2-29. MPUCTRL Register ....................2-30. MPUNUMBER Register List of Figures SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 29 ..................... 4-34. LDODPCAL Register ......................4-35. SDPMST Register ....................4-36. RESBEHAVCTL Register ......................4-37. HSSR Register ......................4-38. USBPDS Register SLAU723A – October 2017 – Revised October 2018 List of Figures Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 30 ......................4-83. SRACMP Register ......................4-84. SRPWM Register ......................4-85. SRQEI Register ....................4-86. SREEPROM Register ......................4-87. SRCCM Register List of Figures SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 31 ....................4-132. SCGCEMAC Register ....................... 4-133. DCGCWD Register ....................4-134. DCGCTIMER Register ..................... 4-135. DCGCGPIO Register ..................... 4-136. DCGCDMA Register SLAU723A – October 2017 – Revised October 2018 List of Figures Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 32 ......................4-181. PRUART Register ......................4-182. PRSSI Register ......................4-183. PRI2C Register ......................4-184. PRUSB Register ......................4-185. PREPHY Register List of Figures SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 33 ...................... 6-29. HIBTPCTL Register ..................... 6-30. HIBTPSTAT Register ......................6-31. HIBTPIO Register ....................6-32. HIBTPLOG0 Register ....................6-33. HIBTPLOG1 Register SLAU723A – October 2017 – Revised October 2018 List of Figures Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 34 7-43. BOOTCFG Register ....................7-44. USER_REGn Register ......................7-45. FMPREn Register ......................7-46. FMPPEn Register ....................8-1. µDMA Block Diagram List of Figures SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 35 AES – F9 Operation ................9-9. AES – CBC-MAC Authentication Mode ....................9-10. AES – GCM Operation ....................9-11. AES – CCM Operation SLAU723A – October 2017 – Revised October 2018 List of Figures Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 36 ......................10-26. ADCSAC Register ..................... 10-27. ADCDCISC Register ......................10-28. ADCCTL Register ....................10-29. ADCSSMUX0 Register ....................10-30. ADCSSCTL0 Register List of Figures SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 37 11-22. CANMSGnINT Register ....................11-23. CANMSGnVAL Register ................12-1. Analog Comparator Module Block Diagram .................... 12-2. Structure of Comparator Unit SLAU723A – October 2017 – Revised October 2018 List of Figures Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 38 15-11. System Time Update Using Fine Correction Method ......15-12. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path Correction .................. 15-13. Wake-Up Frame Filter Register Bank List of Figures SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 39 ....................15-59. EMACTIMSECU Register 1002 .................... 15-60. EMACTIMNANOU Register 1003 ....................15-61. EMACTIMADD Register 1004 ..................... 15-62. EMACTARGSEC Register 1005 SLAU723A – October 2017 – Revised October 2018 List of Figures Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 40 .................... 15-108. EPHYRXERCNT Register 1074 ....................15-109. EPHYBISTCR Register 1075 ....................15-110. EPHYLEDCR Register 1077 ....................15-111. EPHYCTL Register 1078 List of Figures SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 41 ....................16-40. EPIRSIZEn Register 1149 ....................16-41. EPIRADDRn Register 1150 ....................16-42. EPIRPSTDn Register 1151 ....................... 16-43. EPISTAT Register 1152 SLAU723A – October 2017 – Revised October 2018 List of Figures Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 42 ....................... 17-24. GPIOCR Register 1227 ....................17-25. GPIOAMSEL Register 1228 ....................17-26. GPIOPCTL Register 1230 ....................17-27. GPIOADCCTL Register 1231 List of Figures SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 43 ..................... 18-26. GPTMTAR Register 1300 ..................... 18-27. GPTMTBR Register 1301 ..................... 18-28. GPTMTAV Register 1302 ..................... 18-29. GPTMTBV Register 1303 SLAU723A – October 2017 – Revised October 2018 List of Figures Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 44 ....................19-39. I2CSACKCTL Register 1370 ....................19-40. I2CFIFODATA Register 1371 ....................19-41. I2CFIFOCTL Register 1372 ..................... 19-42. I2CFIFOSTATUS Register 1374 List of Figures SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 45 21-3. PWM Count Down Mode 1439 ................... 21-4. PWM Count Up/Down Mode 1440 .............. 21-5. PWM Generation Example In Count-Up/Down Mode 1440 SLAU723A – October 2017 – Revised October 2018 List of Figures Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 46 ....................22-13. ONEWIREMIS Register 1518 ....................22-14. ONEWIREICR Register 1519 ....................22-15. ONEWIREDMA Register 1520 ....................22-16. ONEWIREPP Register 1521 List of Figures SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 47 24-13. QEIRIS Register 1584 ......................24-14. QEIISC Register 1585 ..................25-1. SHA/MD5 Module Block Diagram 1587 ....................25-2. SHA/MD5 Polling Mode 1597 SLAU723A – October 2017 – Revised October 2018 List of Figures Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 48 26-31. UARTPCellID1 Register 1669 ....................26-32. UARTPCellID2 Register 1670 ....................26-33. UARTPCellID3 Register 1671 ................... 27-1. USB Module Block Diagram 1673 List of Figures SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 49 27-48. USBTXCSRLn Register (OTG B / Device) 1747 ................27-49. USBTXCSRHn Register (OTG A / Host) 1749 ................27-50. USBTXCSRHn Register (OTG B / Device) 1750 SLAU723A – October 2017 – Revised October 2018 List of Figures Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 50 ....................... 28-4. WDTCTL Register 1803 ....................... 28-5. WDTICR Register 1805 ....................... 28-6. WDTRIS Register 1806 ....................... 28-7. WDTMIS Register 1807 List of Figures SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 51 ....................28-18. WDTPCellID0 Register 1814 ....................28-19. WDTPCellID1 Register 1814 ....................28-20. WDTPCellID2 Register 1815 ....................28-21. WDTPCellID3 Register 1815 SLAU723A – October 2017 – Revised October 2018 List of Figures Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 52 2-21. PRIn Register Field Descriptions .................. 2-22. SWTRIG Register Field Descriptions ......................2-23. SCB Registers ....................2-24. SCB Access Type Codes List of Tables SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 53 4-14. RIS Register Field Descriptions ..................4-15. IMC Register Field Descriptions ..................4-16. MISC Register Field Descriptions ..................4-17. RESC Register Field Descriptions SLAU723A – October 2017 – Revised October 2018 List of Tables Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 54 4-63. PPI2C Register Field Descriptions ..................4-64. PPUSB Register Field Descriptions .................. 4-65. PPEPHY Register Field Descriptions ..................4-66. PPCAN Register Field Descriptions List of Tables SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 55 4-112. RCGCPWM Register Field Descriptions ................. 4-113. RCGCQEI Register Field Descriptions ................. 4-114. RCGCEEPROM Register Field Descriptions ................4-115. RCGCCCM Register Field Descriptions SLAU723A – October 2017 – Revised October 2018 List of Tables Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 56 4-161. Module Power Control ..................4-162. PCWD Register Field Descriptions ....................4-163. Module Power Control ................. 4-164. PCTIMER Register Field Descriptions List of Tables SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 57 4-210. PRSSI Register Field Descriptions ..................4-211. PRI2C Register Field Descriptions ..................4-212. PRUSB Register Field Descriptions .................. 4-213. PREPHY Register Field Descriptions SLAU723A – October 2017 – Revised October 2018 List of Tables Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 58 6-26. HIBTPIO Register Field Descriptions ................6-27. HIBTPLOG0 Register Field Descriptions ................6-28. HIBTPLOG1 Register Field Descriptions ..................6-29. HIBPP Register Field Descriptions List of Tables SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 59 7-45. BOOTCFG Register Field Descriptions ................7-46. USER_REGn Register Field Descriptions .................. 7-47. FMPREn Register Field Descriptions .................. 7-48. FMPPEn Register Field Descriptions SLAU723A – October 2017 – Revised October 2018 List of Tables Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 60 8-46. DMAPCellID0 Register Field Descriptions ................8-47. DMAPCellID1 Register Field Descriptions ................8-48. DMAPCellID2 Register Field Descriptions ................8-49. DMAPCellID3 Register Field Descriptions List of Tables SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 61 10-20. ADCDCISC Register Field Descriptions .................. 10-21. ADCCTL Register Field Descriptions ................10-22. ADCSSMUX0 Register Field Descriptions ................10-23. ADCSSCTL0 Register Field Descriptions SLAU723A – October 2017 – Revised October 2018 List of Tables Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 62 11-19. CANIFnARB1 Register Field Descriptions ................11-20. CANIFnARB2 Register Field Descriptions ................11-21. CANIFnMCTL Register Field Descriptions ................11-22. CANIFnDnn Register Field Descriptions List of Tables SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 63 14-22. DES_DIRTYBITS Register Field Descriptions ....................14-23. DES µDMA Registers ..................14-24. DES µDMA Access Type Codes ................14-25. DES_DMAIM Register Field Descriptions SLAU723A – October 2017 – Revised October 2018 List of Tables Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 64 15-43. EMACADDR1L Register Field Descriptions ................15-44. EMACADDR2H Register Field Descriptions ................15-45. EMACADDR2L Register Field Descriptions ................15-46. EMACADDR3H Register Field Descriptions List of Tables SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 65 15-93. EMACPP Register Field Descriptions 1037 ................15-94. EMACPC Register Field Descriptions 1038 ................15-95. EMACCC Register Field Descriptions 1041 SLAU723A – October 2017 – Revised October 2018 List of Tables Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 66 16-13. EPI Access Type Codes 1123 .................. 16-14. EPICFG Register Field Descriptions 1124 ................16-15. EPIBAUD Register Field Descriptions 1125 List of Tables SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 67 17-13. GPIORIS Register Field Descriptions 1210 ................17-14. GPIOMIS Register Field Descriptions 1211 ................17-15. GPIOICR Register Field Descriptions 1212 SLAU723A – October 2017 – Revised October 2018 List of Tables Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 68 18-8. Counter Values When the Timer is Enabled in PWM Mode 1262 ................... 18-9. Time-out Actions for GPTM Modes 1266 List of Tables SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 69 19-17. I2CMBMON Register Field Descriptions 1355 ................19-18. I2CMBLEN Register Field Descriptions 1356 ................19-19. I2CMBCNT Register Field Descriptions 1357 SLAU723A – October 2017 – Revised October 2018 List of Tables Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 70 20-32. LCDMISCLR Register Field Descriptions 1427 ................... 20-33. LCDIM Register Field Descriptions 1429 ................20-34. LCDIENC Register Field Descriptions 1431 List of Tables SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 71 22-11. ONEWIREMIS Register Field Descriptions 1518 ................22-12. ONEWIREICR Register Field Descriptions 1519 ................. 22-13. ONEWIREDMA Register Field Descriptions 1520 SLAU723A – October 2017 – Revised October 2018 List of Tables Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 72 25-4. Inner Digest Registers 1590 ................25-5. SHA Digest Processed in Three Passes 1592 .................. 25-6. SHA Digest Processed in One Pass 1593 List of Tables SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 73 26-23. UARTPeriphID5 Register Field Descriptions 1661 ................ 26-24. UARTPeriphID6 Register Field Descriptions 1662 ................ 26-25. UARTPeriphID7 Register Field Descriptions 1663 SLAU723A – October 2017 – Revised October 2018 List of Tables Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 74 27-39. USBTXHUBADDRn Register Field Descriptions 1732 ..............27-40. USBTXHUBPORTn Register Field Descriptions 1733 ..............27-41. USBRXFUNCADDRn Register Field Descriptions 1734 List of Tables SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 75 27-88. USBEPCISC Register Field Descriptions 1785 ................27-89. USBDRRIS Register Field Descriptions 1786 ................27-90. USBDRIM Register Field Descriptions 1787 SLAU723A – October 2017 – Revised October 2018 List of Tables Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 76 28-20. WDTPCellID1 Register Field Descriptions 1814 ................28-21. WDTPCellID2 Register Field Descriptions 1815 ................28-22. WDTPCellID3 Register Field Descriptions 1815 List of Tables SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 77 This value in the register bit diagram shows the bit field value after any reset, unless noted. Bit cleared to 0 on chip reset Bit set to 1 on chip reset SLAU723A – October 2017 – Revised October 2018 About This Document Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 78 1011b, and decimal numbers are written without a prefix or suffix. Trademarks SimpleLink is a trademark of Texas Instruments. Arm7, CoreSight are trademarks of Arm Limited. Arm, Cortex, Thumb, PrimeCell are registered trademarks of Arm Limited.
Page 79 ................... Programming Model ....................Memory Model ....................Exception Model ....................Fault Handling ..................Power Management ................... Instruction Set Summary SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 80: Introduction
This chapter provides information on the MSP432E4 implementation of the Cortex-M4F processor, including the programming model, the memory model, the exception model, fault handling, and power management. ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 81: Cpu Block Diagram
Figure 1-1 shows the CPU block diagram. Figure 1-1. CPU Block Diagram SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 82: Tpiu Block Diagram
Trace Port (serializer) Slave Interface (SWO) Port Advance Peripheral Bus Slave (APB) Port Interface Figure 1-2. TPIU Block Diagram ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 83: Programming Model
Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software. SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 84: Summary Of Processor Mode, Privilege Level, And Stack Use
Privileged or unprivileged Main stack or process stack Handler Exception handlers Always privileged Main stack See CONTROL (Figure 1-12). ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 85: Cortex-M4F Register Set
Complex bit access types are encoded to fit into small table cells. Table 1-3 lists the codes that are used for access types in this section. SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 86: R_0 To R_12 Register
Table 1-5. SP Register Field Descriptions Field Type Reset Description 31:0 This field is the address of the stack pointer. ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 87: Lr Register
R/W-X Table 1-7. PC Register Field Descriptions Field Type Reset Description 31:0 This field is the current program address. SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 88: Psr Register Combinations
The processor ignores writes to the IPSR bits. Reads of the EPSR bits return zero, and the processor ignores writes to these bits. ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 89: Psr Register
Cortex-M4 Devices Generic User Guide for more information. The value of this field is only meaningful when accessing PSR or APSR. SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 90 0Eh = PendSV 0Fh = SysTick 10h = Interrupt Vector 0 11h = Interrupt Vector 1 ..81h = Interrupt Vector 113 ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 91: Primask Register
RESERVED PRIMASK R-0h R/W-0h Table 1-10. PRIMASK Register Field Descriptions Field Type Reset Description 31:1 RESERVED PRIMASK Priority Mask SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 92: Faultmask Register
FAULTMASK Fault Mask. The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 93: Basepri Register
The PRIMASK register can be used to mask all exceptions with programmable priority levels. Higher priority exceptions have lower priority levels. RESERVED SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 94: Control Register
Active Stack Pointer In Handler mode. This bit reads as zero and ignores writes. The Cortex-M4F updates this bit automatically on exception return. TMPL Thread Mode Privilege Level ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 95: Fpsc Register
0 was last written to this bit. Underflow Cumulative Exception. When set, indicates this exception has occurred since 0 was last written to this bit. SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 96 Invalid Operation Cumulative Exception. When set, indicates this exception has occurred since 0 was last written to this bit. ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 97: Memory Map
GPIO Port C 0x4000.7000 0x4000.7FFF GPIO Port D 0x4000.8000 0x4000.8FFF SSI0 0x4000.9000 0x4000.9FFF SSI1 0x4000.A000 0x4000.AFFF SSI2 0x4000.B000 0x4000.BFFF SSI3 SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 98 GPIO Port F (AHB aperture) 0x4005.E000 0x4005.EFFF GPIO Port G (AHB aperture) 0x4005.F000 0x4005.FFFF GPIO Port H (AHB aperture) ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 99 Reserved (4KB) 0x4403.2000 0x4403.3FFF Reserved (8KB) 0x4403.4000 0x4403.5FFF SHA/MD5 0x4403.6000 0x4403.7FFF 0x4403.8000 0x4403.9FFF 0x4403.A000 0x4403.EFFF Reserved 0x4403.F000 0x4403.FFFF Reserved (4KB) SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 100 XN attribute. MSP432E4 devices may have reserved memory areas within the address ranges listed in Table 1-16 (see Table 1-15 for more information). ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 101: Memory Access Behavior
MPU region or regions, if the MPU configuration code was accessed using a branch or call. If the MPU configuration code is entered using exception mechanisms, then an ISB instruction is not SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 102: Sram Memory Bit-Banding Regions
Direct accesses to this memory range behave as peripheral 0x4000.0000 0x400F.FFFF Peripheral bit-band region memory accesses, but this region is also bit addressable through bit-band alias. ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 103: Bit-Band Mapping
The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000: 0x2200.001C = 0x2200.0000+ (0 × 32) + (7 × 4) Figure 1-14. Bit-Band Mapping SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 104: Data Storage
The pairs of Load-Exclusive and Store-Exclusive instructions are: • The word instructions LDREX and STREX ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 105: Exception Model
Nonmaskable Interrupt (NMI), and a Hard Fault, in that order. The default priority is 0 for all the programmable priorities. SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 106: 1.6.2 Exception Types
This fault can be enabled or disabled. ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 107 – Reserved 0 is the default priority for all the programmable priorities. Section 1.6.4. See SYSPRI1 in Section 2.5.8. SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 108 The least significant bit of each vector must be 1, indicating that the exception handler is Thumb code. ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 109: Vector Table
For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 110 Thread mode or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 111: Exception Stack Frame
SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 112: Exception Return Behavior
Return to thread mode. 0xFFFF.FFFD Exception return uses nonfloating-point state from PSP. Execution uses PSP after return. 0xFFFF.FFFE to 0xFFFF.FFFF Reserved ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 113: Fault Handling
Section 1.6. SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 114: Fault Status And Fault Address Registers
This section describes the mechanisms for entering sleep mode and the conditions for waking up from sleep mode, both of which apply to sleep mode and deep-sleep mode. ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 115: Instruction Set Summary
Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 1-23 lists the supported instructions. SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 116: Cortex-M4F Instruction Summary
LDREXH Rt, [Rn] Load register exclusive with halfword – LDRH, LDRHT Rt, [Rn, #offset] Load register with halfword – ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 117 – SHADD16 {Rd,} Rn, Rm Signed halving add 16 – SHADD8 {Rd,} Rn, Rm Signed halving add 8 – SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 118 {Rd,} Rn, Rm,{,ROR #} Extend 16 bits to 32 and add – SXTB16 {Rd,} Rm {,ROR #n} Signed extend byte 16 – ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 119 Floating-point add – Compare two floating-point registers, or one VCMP.F32 Sd, <Sm | #0.0> FPSCR floating-point register and zero SLAU723A – October 2017 – Revised October 2018 ® Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 120 Stores an extension register to memory – VSUB.F<32|64> {Sd,} Sn, Sm Floating-point subtract – – Wait for event – – Wait for interrupt – ® SLAU723A – October 2017 – Revised October 2018 Cortex -M4F Processor Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 121 Page ..................... Introduction ..................Functional Description ..................... SysTick Registers ....................NVIC Registers ....................SCB Registers ....................MPU Registers ....................FPU Registers SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 122: Core Peripheral Register Regions
An internal clock source control based on missing/meeting durations. The COUNT bit in the STCTRL control and status register can be used to determine if an action completed within a set duration, as Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 123 NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt. SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 124 The Cortex-M4 MPU memory map is unified, meaning that instruction accesses and data accesses have the same region settings. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 125: Memory Attributes Summary
; Region Size and Enable STR R4, [R0, #0x4] ; Region Base Address STRH R3, [R0, #0xA] ; Region Attribute ORR R2, #1 ; Enable SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 126 Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the field must be configured to 0x00, otherwise the MPU behavior is unpredictable. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 127: Srd Use Example
Table 2-4 for the encoding of the Normal Shareable AA and BB bits. The MPU ignores the value of this bit. SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 128: Cache Policy For Memory Attribute Encoding
This section describes the Floating-Point Unit (FPU) and the registers it uses. The FPU provides: • 32-bit instructions for single-precision (C float) data-processing operations • Combined multiply and accumulate instructions for increased precision (Fused MAC) Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 129: Fpu Register Bank
For example, you can access the least significant half of the value in D6 by accessing S12, and the most significant half of the elements by accessing S13. SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 130 The Cortex-M4FPU supports fused MAC operations as described in the IEEE standard. For complete implementation of the IEEE 754-2008 standard, floating-point functionality must be augmented with library functions. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 131: Nan Handling
2008 standard predicates to Arm conditions, see the Arm Architecture Reference Manual. The flags used are chosen so that subsequent conditional execution of Arm instructions can test the predicates defined in the IEEE standard. SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 132 ; Write back the modified value to the CPACR STR R1, [R0]; wait for store to complete ;reset pipeline now the FPU is enabled Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 133: Systick Registers
Access Type Code Description Read Type Read Write Type Write Write Reset or Default Value Value after reset or the default value SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 134: Stctrl Register
0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 135: Streload Register
31-24 RESERVED 23-0 RELOAD Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 136: Stcurrent Register
This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 137: Nvic Registers
0x42C PRI11 Interrupt 44-47 Priority Section 2.4.6 0x430 PRI12 Interrupt 48-51 Priority Section 2.4.6 0x434 PRI13 Interrupt 52-55 Priority Section 2.4.6 SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 138: Nvic Access Type Codes
Access Type Code Description Read Type Read Write Type Write Write Reset or Default Value Value after reset or the default value Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 139: En0 To En3 Registers
0x0 = On a read, indicates the interrupt is disabled. On a write, no effect. 0x1 = On a read, indicates the interrupt is enabled. On a write, enables the interrupt. SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 140: Disn Register
0x1 = On a read, indicates the interrupt is enabled.On a write, clears the corresponding INT[n] bit in the EN0 register, disabling interrupt [n]. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 141: Pendn Register
0x1 = On a read, indicates that the interrupt is pending.On a write, the corresponding interrupt is set to pending even if it is disabled. SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 142: Unpendn Register
INT[n] bit in the PEND0 register, so that interrupt [n] is no longer pending.Setting a bit does not affect the active state of the corresponding interrupt. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 143: Activen Register
Interrupt Active 0x0 = The corresponding interrupt is not active. 0x1 = The corresponding interrupt is active, or active and pending. SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 144 PRIn Register Bit Field Interrupt Bits 31:29 Interrupt [4n+3] Bits 23:21 Interrupt [4n+2] Bits 15:13 Interrupt [4n+1] Bits 7:5 Interrupt [4n] Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 145: Prin Register
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 146: Swtrig Register
Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 147: Scb Registers
Read Type Read Write Type Write 1 to clear Write Reset or Default Value Value after reset or the default value SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 148: Actlr Register
DISFOLD bit before executing the task, to disable IT folding. DISWBUF Disable Write Buffer DISMCYC Disable Interrupts of Multiple Cycle Instructions Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 149: Cpuid Register
Table 2-26. CPUID Register Field Descriptions Field Type Reset Description 31-24 0x41 Implementer Code 23-20 Variant Number 19-16 Constant 15-4 PARTNO 0xC24 Part Number Revision Number SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 150: Intctrl Register
Debug Interrupt Handling This bit is only meaningful in Debug mode and reads as zero when the processor is not in Debug mode. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 151 Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers (see ). SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 152: Vtable Register
Because there are 112 interrupts, the offset must be aligned on a 1024-byte boundary. RESERVED Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 153: Apint Register
On a read, 0xFA05 is returned. ENDIANESS Data Endianess The MSP432E4 implementation uses only little-endian mode so this is cleared to 0. 14-11 RESERVED SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 154 This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 155: Sysctrl Register
SLEEPEXIT Sleep on ISR Exit Setting this bit enables an interrupt-driven application to avoid returning to an empty main application. RESERVED SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 156: Cfgctrl Register
Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of whether UNALIGNED is set. RESERVED MAINPEND Allow Main Interrupt Trigger BASETHR Thread State Control Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 157: Syspri1 Register
This field configures the priority level of the memory management fault. Configurable priority values are in the range 0-7, with lower values having higher priority. RESERVED SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 158: Syspri2 Register
This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority. 28-0 RESERVED Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 159: Syspri3 Register
This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. RESERVED SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 160: Syshndctrl Register
BUSP Bus Fault Pending This bit can be modified to change the pending status of the bus fault exception. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 161: Syshndctrl Register Field Descriptions
This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 162: Faultstat Register
R/W1C-0x0 R/W1C-0x0 R/W1C-0x0 R/W1C-0x0 R/W1C-0x0 MMARV RESERVED MLSPERR MSTKE MUSTKE RESERVED DERR IERR R/W1C-0x0 R-0x0 R/W1C-0x0 R/W1C-0x0 R/W1C-0x0 R-0x0 R/W1C-0x0 R/W1C-0x0 Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 163: Faultstat Register Field Descriptions
FAULTADDR register. This bit is cleared by writing a 1 to it. SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 164 MMADDR register. This bit is cleared by writing a 1 to it. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 165: Hfaultstat Register
PC value stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by writing a 1 to it. RESERVED SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 166: Mmaddr Register
When the MMARV bit of MFAULTSTAT is set, this field holds the address of the location that generated the memory management fault. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 167: Faultaddr Register
When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 168: Mpu Registers
Access Type Code Description Read Type Read Write Type Write Write Reset or Default Value Value after reset or the default value Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 169: Mputype Register
The MPU memory map is unified and is described by the DREGION field. 15-8 DREGION Number of D Regions RESERVED SEPARATE Separate or Unified MPU SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 170: Mpuctrl Register
Return to Summary Table. Figure 2-29. MPUCTRL Register RESERVED R-0x0 RESERVED R-0x0 RESERVED R-0x0 RESERVED PRIVDEFEN HFNMIENA ENABLE R-0x0 R/W-0x0 R/W-0x0 R/W-0x0 Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 171: Mpuctrl Register Field Descriptions
ENABLE MPU Enable When the MPU is disabled and the HFNMIENA bit is set, the resulting behavior is unpredictable. SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 172: Mpunumber Register
MPU Region to Access This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers. The MPU supports eight memory regions. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 173: Mpubasen Register
To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. VALID Region Number Valid This bit is always read as 0. RESERVED SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 174 On a write, contains the value to be written to the MPUNUMBER register. On a read, returns the current region number in the MPUNUMBER register. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 175: Mpuattrn Register
Figure 2-32. MPUATTRn Register RESERVED RESERVED R-0x0 R/W-0x0 R-0x0 R/W-0x0 RESERVED R-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 RESERVED SIZE ENABLE R-0x0 R/W-0x0 R/W-0x0 SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 176: Mpuattrn Register Field Descriptions
The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. Refer to Table 2-47 for more information. ENABLE Region Enable Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 177: Fpu Registers
Access Type Code Description Read Type Read Write Type Write Reset or Default Value Value after reset or the default value SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 178: Cpac Register
0x1 = Privileged Access Only. An unprivileged access generates a NOCP fault. 0x2 = Reserved. The result of any access is unpredictable. 0x3 = Full Access 19-0 RESERVED Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 179: Fpcc Register
THREAD Thread Mode When set, mode was Thread Mode when the floating-point stack frame was allocated. RESERVED SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 180 When set, Lazy State preservation is active. Floating-point stack frame has been allocated but saving state to it has been deferred. Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 181: Fpca Register
Type Reset Description 31-3 ADDRESS Address The location of the unpopulated floating-point register space allocated on an exception stack frame. RESERVED SLAU723A – October 2017 – Revised October 2018 Cortex-M4 Peripherals Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 182: Fpdsc Register
0x1 = Round toward Plus Infinity (RP) mode 0x2 = Round toward Minus Infinity (RM) mode 0x3 = Round toward Zero (RZ) mode 21-0 RESERVED Cortex-M4 Peripherals SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 183 I/O pin observation and control, scan testing, and debugging..........................Topic Page ..................... Introduction ....................Block Diagram ..................Functional Description ................Initialization and Configuration ..................Register Descriptions SLAU723A – October 2017 – Revised October 2018 JTAG Interface Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 184: Jtag Module Block Diagram
See the Arm Debug Interface V5 Architecture Specification for more information on the Arm JTAG controller. Block Diagram Figure 3-1 shows the block diagram of the JTAG module. Figure 3-1. JTAG Module Block Diagram JTAG Interface SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 185: Jtag Port Pins State After Por Or Rst Assertion
Internal Pulldown Drive Strength Drive Value Input Enabled Disabled Input Enabled Disabled Input Enabled Disabled Output Enabled Disabled 2-mA driver Hi-Z SLAU723A – October 2017 – Revised October 2018 JTAG Interface Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 186 Thus, during board layout, designers should not designate the TDO pin as a GPIO in sensitive applications where the possibility of toggling could affect the design. JTAG Interface SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 187: Test Access Port State Machine
In addition, because the JTAG module has integrated Arm Serial Wire Debug, the method for switching between these two operational modes is described below. SLAU723A – October 2017 – Revised October 2018 JTAG Interface Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 188 1. Assert and hold the RST signal. 2. Apply power to the device. 3. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence on Section 3.3.4.4.1. JTAG Interface SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 189 To verify that the DAP has switched to the Serial Wire Debug (SWD) operating mode, perform a SWD READID operation. The ID value can be compared against the device's known ID to verify the switch. SLAU723A – October 2017 – Revised October 2018 JTAG Interface Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 190: Jtag Instruction Register Commands
Connects TDI to TDO through a single Shift Register chain. Defaults to the BYPASS instruction to ensure that TDI is always connected to All Others Reserved TDO. JTAG Interface SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 191 IDCODE is the default instruction loaded into the JTAG Instruction Register when a Power- On-Reset (POR) is asserted, or the Test-Logic-Reset state is entered. See Section 3.5.2.1 for more information. SLAU723A – October 2017 – Revised October 2018 JTAG Interface Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 192: Idcode Register Format
TAP controller, new data can be preloaded into the chain for use with the EXTEST instruction. The EXTEST instruction forces data out of the controller. JTAG Interface SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 193: Boundary Scan Register Format
The format for the 35-bit ABORT Data Register defined by Arm is described in the Arm Debug Interface V5 Architecture Specification. SLAU723A – October 2017 – Revised October 2018 JTAG Interface Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 194 Configurable features include reset control, NMI operation, power control, clock control, and low-power modes..........................Topic Page ..................Functional Description .................. System Control Registers ........... Cryptographic System Control (CCM) Registers System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 195: Reset Sources
Pin configuration only SYSRESREQ bit in the APINT register Software system reset request using the VECTRESET bit in the APINT register SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 196 3. When initialization is complete, the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 197: Basic Rst Configuration
C components define the power-on delay. MSP432E4 Microcontroller NOTE: R = 0 to 100 kΩ Figure 4-1. Basic RST Configuration SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 198: External Circuitry To Extend Por
If the BOR field is set to 0x0 or 0x1, then the brownout detection circuit performs its default operation upon assertion, which is issuing an interrupt. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 199 3. The internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter. 4. Execution begins. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 200 4. Execution begins. For more information on the Watchdog Timer module, see Chapter System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 201 17.5.20). The active sense of the NMI signal is high; asserting the enabled NMI signal above V initiates the NMI interrupt sequence. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 202: Power Architecture
Analog Circuits VDDA GNDA The VDDA voltage source is typically connected to a filtered voltage source or regulator. Figure 4-4. Power Architecture System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 203 The HIB LFIOSC is a different clock source than the LFIOSC. See the device-specific data sheet for more information on frequency range. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 204: Clock Source Options
Some peripheral clock sources may not be present on your specific device. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 205: Main Clock Tree
UART, SSI, Timers, ADC, WDT mode clock gate RCGC SCGC DCGC Mode is either run/sleep (RS) or deep sleep (DS). Figure 4-5. Main Clock Tree SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 206 Four clock inputs are driven into the Ethernet MAC when the MII configuration is enabled. The clocks are described as follows (see Section 15.3.1.2 for more information): System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 207 GPIO signal and has the electrical characteristics of a GPIO (see the device-specific data sheet). SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 208: System Clock Frequency
1. The MOSCFAIL bit in the RESC register is set. 2. The system clock is switched from the main oscillator to the PIOSC. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 209: Examples Of System Clock Frequencies
The Crystal Frequency column specifies the input crystal frequency, and the PLL Frequency column lists the PLL frequency given the values of MINT and N, when Q = 0. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 210: Actual Pll Frequency
Run mode (see Section 4.1.6.1) • Sleep mode (see Section 4.1.6.2) • Deep-sleep mode (see Section 4.1.6.3) • Hibernation mode (see Section 4.1.6.5) System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 211 Additional sleep modes are available that lower the power consumption of the SRAM and flash memory. However, the lower power consumption modes have slower sleep and wake-up times. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 212 This situation can be avoided by programming the MOSC as the run and sleep clock source in the RSCLKCFG register before entering deep-sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 213: Module Clock Selection
LDO Sleep Power Calibration (LDOSPCAL): Provides factory recommendations for the LDO value in sleep mode • LDO Deep-Sleep Power Calibration (LDODPCAL): Provides factory recommendations for the LDO SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 214: Peripheral Memory Power Control
NOTE: While the device is connected through JTAG, the LDO control settings for sleep and deep- sleep modes are not available and cannot be applied. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 215: Maximum System Clock And Piosc Frequency With Respect To Ldo Voltage
There is no mechanism to clear the bits; they are overwritten on the next event. The data is real time, and no event registers that information. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 216 When the return-to-factory settings sequence is completed, the CDOFF field of the HSSR register is written with 0x00.0000, indicating a successful completion and activating a system reset. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 217: System Control Registers
LCD Memory Power Control Section 4.2.37 0x298 CAN0PDS CAN 0 Power Domain Status Section 4.2.38 0x29C CAN0MPC CAN 0 Memory Power Control Section 4.2.39 SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 218 0x600 RCGCWD Watchdog Timer Run Mode Clock Gating Control Section 4.2.85 0x604 RCGCTIMER 16/32-BitGeneral-Purpose Timer RunMode Clock Gating Control Section 4.2.86 System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 219 Section 4.2.130 0x810 DCGCEPI EPI Deep-Sleep Mode Clock Gating Control Section 4.2.131 0x814 DCGCHIB Hibernation Deep-Sleep Mode Clock Gating Control Section 4.2.132 SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 220 Inter-Integrated Circuit Peripheral Ready Section 4.2.177 0xA28 PRUSB Universal Serial Bus Peripheral Ready Section 4.2.178 0xA30 PREPHY Ethernet PHY Peripheral Ready Section 4.2.179 System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 221: System Control Access Type Codes
Read Write Type Write 1C W 1 to clear Write Reset or Default Value Value after reset or the default value SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 222: Did0 Register
The value of the CLASS field is encoded as follows (all other encodings are reserved): 0x0C = MSP432E4 microcontrollers System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 223 0x0 = Initial device, or a major revision update. 0x1 = First metal layer change. 0x2 = Second metal layer change..and so on. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 224: Did1 Register
(all other encodings are reserved): 0x0 = Commercial temperature range 0x1 = Industrial temperature range 0x2 = Extended temperature range System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 225 (all other encodings are reserved): 0x0 = Engineering Sample (unqualified) 0x1 = Pilot Production (unqualified) 0x2 = Fully Qualified SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 226: Ptboctl Register
This field determines the action to take on the event. 0x0 = No Action 0x1 = System control interrupt 0x2 = NMI 0x3 = Reset System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 227: Ris Register
0x0 = The main oscillator has not failed. 0x1 = The MOSCIM bit in the MOSCCTL register is set and the main oscillator has failed. RESERVED SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 228 1 to the BORMIS bit in the MISC register. 0x0 = A brownout condition is not currently active. 0x1 = A brownout condition is currently active. RESERVED System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 229: Imc Register
0x1 = An interrupt is sent to the interrupt controller when the BORRIS bit in the RIS register is set. RESERVED SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 230: Misc Register
Writing 1 to this bit clears it and also the MOFRIS bit in the RIS register. RESERVED System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 231 Writing 1 to this bit clears it and also the BORRIS bit in the RIS register. RESERVED SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 232: Resc Register
0x1 = When read, this bit indicates that a HSSR request has generated a reset. 11-6 RESERVED System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 233 Writing 0 to this bit clears it. 0x1 = When read, this bit indicates that an external reset (RST assertion) has caused a reset event. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 234: Pwrtc Register
R/W1C Under BOR Status 0x0 = VDD has not tripped undervoltage BOR comparison. 0x1 = VDD has tripped undervoltage BOR comparison. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 235: Nmic Register
Watch Dog Timer (WDT) 0 NMI 0x0 = No WDT 0 time-out has occurred. 0x1 = An NMI has occurred due to a WDT0 time-out event. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 236 External Pin NMI 0x0 = No NMI pin event has occurred. 0x1 = The NMI pin was asserted by external hardware. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 237: Moscctl Register
0x1 = This bit should be set when a crystal or external oscillator is not connected to the OSC0 and OSC1 inputs to reduce power consumption. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 238 CVAL Clock Validation for MOSC 0x0 = The MOSC monitor circuit is disabled. 0x1 = The MOSC monitor circuit is enabled. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 239: Rsclkcfg Register
0x0 = Clock source is specified by the OSCSRC field. 0x1 = Clock source is specified by the PLL. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 240 This field specifies the system clock divisor value for the PLL. This field is used when the USEPLL bit is 1. / (PSYSDIV + 1) syclk System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 241: Memtim0 Register
EBCHT R-0x0 R/W-0x0 EBCHT EBCE RESERVED R/W-0x0 R/W-0x1 R-0x0 R/W-0x0 RESERVED FBCHT R/W-0x0 R/W-0x0 FBCHT FBCE RESERVED R/W-0x0 R/W-0x1 R/W-0x1 R/W-0x0 SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 242: Memtim0 Register Field Descriptions
0x0 = Flash clock rising aligns with system clock rising. 0x1 = Flash clock rising aligns with system clock falling. RESERVED System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 243 0x3 = 3 wait states 0x4 = 4 wait states 0x5 = 5 wait states 0x6 = 6 wait states 0x7 = 7 wait states SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 244: Altclkcfg Register
0x0 = Precision Internal Oscillator (PIOSC) 0x1 = Reserved 0x2 = Reserved 0x3 = Hibernation module real-time clock output (RTCOSC) 0x4 = Low-frequency internal oscillator (LFIOSC) System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 245: Dsclkcfg Register
Table. Figure 4-20. DSCLKCFG Register PIOSCPD MOSCDPD RESERVED R/W-0x0 R/W-0x0 R-0x0 DSOSCSRC RESERVED R/W-0x0 R-0x0 RESERVED DSSYSDIV R-0x0 R/W-0x0 DSSYSDIV R/W-0x0 SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 246: Dsclkcfg Register Field Descriptions
Q post-divider bit field in the PLLFREQ1 register may need to be adjusted to keep the system clock frequency within the maximum clock frequency before entering deep sleep. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 247: Divsclk Register
The output clock frequency is equal to the source clock frequency divided by the DIV field value plus 1. 0x0 = Divided by 1 0x1 = Divided by 2 SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 248: Sysprop Register
0x1 = The SRAMPM fields can be configured to put the SRAM into standby mode while in sleep or deep-sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 249 This bit indicates if the FPU is present in the Cortex -M4 core. 0x0 = FPU is not present. 0x1 = FPU is present. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 250: Piosccal Register
0x1 = Updates the PIOSC trim value with the UT bit or the DT bit in the PIOSCSTAT register. Used with UTEN. RESERVED User Trim Value. User trim value that can be loaded into the PIOSC. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 251: Pioscstat Register
Calibration Trim Value. This field contains the trim value from the last calibration operation. After factory calibration, CT and DT are the same. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 252: Pllfreq0 Register
MFRAC PLL M Fractional Value MINT PLL M Integer Value. This field contains the integer value of the PLL M value. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 253: Pllfreq1 Register
PLL Q Value. This field contains the PLL Q value. RESERVED PLL N Value. This field contains the PLL N value. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 254: Pllstat Register
LOCK PLL Lock 0x0 = The PLL is unpowered or is not yet locked. 0x1 = The PLL powered and locked. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 255: Slppwrcfg Register
0x3 = Low-power mode. SRAM is placed in low-power mode. This mode provides the slowest time to sleep and wakeup but the lowest power consumption while in sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 256: Dslppwrcfg Register
This mode provides the lowers power consumption but requires more time to come out of deep-sleep mode. 0x3 = Reserved RESERVED System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 257: Dslppwrcfg Register Field Descriptions
0x3 = Low Power Mode. SRAM is placed in low-power mode. This mode provides the slowest time to sleep and wakeup but the lowest power consumption while in deep-sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 258: Nvmstat Register
31-1 RESERVED 32 Word Flash Write Buffer Available. When set, indicates that the 32-word flash memory write buffer feature is available. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 259: Ldospctl Register
0x15 = 1.05 V 0x16 = 1.10 V 0x17 = 1.15 V 0x18 = 1.20 V All other values are reserved. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 260: Ldospcal Register
LDOSPCTL register when not using the PLL. This value provides the lowest recommended LDO output voltage for use without the PLL. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 261: Ldodpctl Register
0x15 = 1.05 V 0x16 = 1.10 V 0x17 = 1.15 V 0x18 = 1.20 V All other values are reserved. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 262: Ldodpcal Register
LDODPCTL register when not using the PLL. This value provides the lowest recommended LDO output voltage for use with the low- frequency internal oscillator. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 263: Sdpmst Register
SRAM or flash memory into a lower-power mode is currently active as configured by the SLPPWRCFG register. 15-8 RESERVED SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 264 0x1 = An error has occurred because software has requested an SRAM power down mode that is not available using the SRAMPM field in the SLPPWRCFG or the DSLPPWRCFG register. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 265: Resbehavctl Register
0x0 = Reserved. Default operation is performed. 0x2 = External RST assertion issues a system reset. 0x3 = External RST assertion issues a simulated POR sequence (default). SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 266: Hssr Register
If CDOFF = 0xFFFFFF, the previous request through HSSR did not complete due to an error. Otherwise, CDOFF contains the offset for a data structure in SRAM. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 267: Usbpds Register
0x2 = Reserved 0x3 = Array on PWRSTAT Power Domain Status 0x0 = Off 0x1 = Reserved 0x2 = Reserved 0x3 = On SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 268: Usbmpc Register
Allows multiple levels of power control in the peripheral SRAM space. 0x0 = Array off 0x1 = SRAM retention 0x2 = Reserved 0x3 = Array on System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 269: Emacpds Register
0x2 = Reserved 0x3 = Array on PWRSTAT Power Domain Status 0x0 = Off 0x1 = Reserved 0x2 = Reserved 0x3 = On SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 270: Emacmpc Register
0x0 = Array off. Array off mode is supported only when the P0 bit of the PCEMAC register at offset 0x99C is set to 0. 0x1 = Reserved 0x2 = Reserved 0x3 = Array on System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 271: Lcdpds Register
0x2 = Reserved 0x3 = Array on PWRSTAT Power Domain Status 0x0 = Off 0x1 = Reserved 0x2 = Reserved 0x3 = On SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 272: Lcdmpc Register
Allows multiple levels of power control in peripheral's SRAM space 0x0 = Array off 0x1 = Reserved 0x2 = Reserved 0x3 = Array on System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 273: Can0Pds Register
0x2 = Reserved 0x3 = Array on PWRSTAT Power Domain Status 0x0 = Off 0x1 = Reserved 0x2 = Reserved 0x3 = On SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 274: Can0Mpc Register
Allows multiple levels of power control in peripheral SRAM space. 0x0 = Array off 0x1 = Reserved 0x2 = Reserved 0x3 = Array on System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 275: Can1Pds Register
0x2 = Reserved 0x3 = Array on PWRSTAT Power Domain Status 0x0 = Off 0x1 = Reserved 0x2 = Reserved 0x3 = On SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 276: Can1Mpc Register
Allows multiple levels of power control in peripheral SRAM space. 0x0 = Array off 0x1 = Reserved 0x2 = Reserved 0x3 = Array on System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 277: Ppwd Register
0x1 = Watchdog module 1 is present. Watchdog Timer 0 Present 0x0 = Watchdog module 0 is not present. 0x1 = Watchdog module 0 is present. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 278: Pptimer Register
16/32-Bit General-Purpose Timer 0 Present 0x0 = 16/32-bit general-purpose timer module 0 is not present. 0x1 = 16/32-bit general-purpose timer module 0 is present. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 279: Ppgpio Register
0x1 = GPIO port K is present. GPIO Port J Present 0x0 = GPIO port J is not present. 0x1 = GPIO port J is present. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 280: Ppgpio Register Field Descriptions
0x1 = GPIO port B is present. GPIO Port A Present 0x0 = GPIO port A is not present. 0x1 = GPIO port A is present. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 281: Ppdma Register
Type Reset Description 31-1 RESERVED µDMA Module Present 0x0 = µDMA module is not present. 0x1 = µDMA module is present. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 282: Ppepi Register
Type Reset Description 31-1 RESERVED EPI Module Present 0x0 = EPI module is not present. 0x1 = EPI module is present. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 283: Pphib Register
Type Reset Description 31-1 RESERVED Hibernation Module Present 0x0 = Hibernation module is not present. 0x1 = Hibernation module is present. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 284: Ppuart Register
0x1 = UART module 1 is present. UART Module 0 Present 0x0 = UART module 0 is not present. 0x1 = UART module 0 is present. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 285: Ppssi Register
0x1 = SSI module 1 is present. SSI Module 0 Present 0x0 = SSI module 0 is not present. 0x1 = SSI module 0 is present. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 286: Ppi2C Register
0x1 = I2C module 1 is present. I2C Module 0 Present 0x0 = I2C module 0 is not present. 0x1 = I2C module 0 is present. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 287: Ppusb Register
Type Reset Description 31-1 RESERVED USB Module Present 0x0 = USB module is not present. 0x1 = USB module is present. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 288: Ppephy Register
31-1 RESERVED Ethernet PHY Module Present 0x0 = Ethernet PHY module is not present. 0x1 = Ethernet PHY module is present. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 289: Ppcan Register
0x1 = CAN module 1 is present. CAN Module 0 Present 0x0 = CAN module 0 is not present. 0x1 = CAN module 0 is present. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 290: Ppadc Register
0x1 = ADC module 1 is present. ADC Module 0 Present 0x0 = ADC module 0 is not present. 0x1 = ADC module 0 is present. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 291: Ppacmp Register
31-1 RESERVED Analog Comparator Module Present 0x0 = Analog comparator module is not present. 0x1 = Analog comparator module is present. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 292: Pppwm Register
31-1 RESERVED PWM Module 0 Present 0x0 = PWM module 0 is not present. 0x1 = PWM module 0 is present. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 293: Ppqei Register
31-1 RESERVED QEI Module 0 Present 0x0 = QEI module 0 is not present. 0x1 = QEI module 0 is present. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 294: Ppeeprom Register
Reset Description 31-1 RESERVED EEPROM 0 Module Present 0x0 = EEPROM module is not present. 0x1 = EEPROM module is present. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 295: Ppccm Register
0x0 = The CRC, AES, DES, and SHA/MD modules are not present. 0x1 = The CRC, AES, DES, and SHA/MD modules are present. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 296: Pplcd Register
Type Reset Description 31-1 RESERVED LCD Module Present 0x0 = LCD module is not present. 0x1 = LCD module is present. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 297: Ppowire Register
Type Reset Description 31-1 RESERVED 1-Wire Module Present 0x0 = 1-Wire module is not present. 0x1 = 1-Wire module is present. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 298: Ppemac Register
Ethernet Controller Module Present 0x0 = Ethernet Controller MAC module is not present. 0x1 = Ethernet Controller MAC module is present. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 299: Ppprb Register
Type Reset Description 31-1 RESERVED PRB Module Present 0x0 = PRB module is not present. 0x1 = PRB module is present. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 300: Srwd Register
0x1 = Watchdog module 1 is reset. Watchdog Timer 0 Software Reset 0x0 = Watchdog module 0 is not reset. 0x1 = Watchdog module 0 is reset. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 301: Srtimer Register
16/32-Bit General-Purpose Timer 0 Software Reset 0x0 = 16/32-bit general-purpose timer module 0 is not reset. 0x1 = 16/32-bit general-purpose timer module 0 is reset. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 302: Srgpio Register
0x1 = GPIO port N is reset. GPIO Port M Software Reset 0x0 = GPIO port M is not reset. 0x1 = GPIO port M is reset. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 303 0x1 = GPIO port B is reset. GPIO Port A Software Reset 0x0 = GPIO port A is not reset. 0x1 = GPIO port A is reset. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 304: Srdma Register
Reset Description 31-1 RESERVED µDMA Module Software Reset 0x0 = µDMA module is not reset. 0x1 = µDMA module is reset. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 305: Srepi Register
Reset Description 31-1 RESERVED EPI Module Software Reset 0x0 = EPI module is not reset. 0x1 = EPI module is reset. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 306: Srhib Register
Reset Description 31-1 RESERVED Hibernation Module Software Reset 0x0 = Hibernation module is not reset. 0x1 = Hibernation module is reset. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 307: Sruart Register
0x1 = UART module 2 is reset. UART Module 1 Software Reset 0x0 = UART module 1 is not reset. 0x1 = UART module 1 is reset. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 308 Description UART Module 0 Software Reset 0x0 = UART module 0 is not reset. 0x1 = UART module 0 is reset. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 309: Srssi Register
0x1 = SSI module 1 is reset. SSI Module 0 Software Reset 0x0 = SSI module 0 is not reset. 0x1 = SSI module 0 is reset. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 310: Sri2C Register
0x1 = I2C module 4 is reset. I2C Module 3 Software Reset 0x0 = I2C module 3 is not reset. 0x1 = I2C module 3 is reset. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 311 0x1 = I2C module 1 is reset. I2C Module 0 Software Reset 0x0 = I2C module 0 is not reset. 0x1 = I2C module 0 is reset. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 312: Srusb Register
Reset Description 31-1 RESERVED USB Module Software Reset 0x0 = USB module is not reset. 0x1 = USB module is reset. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 313: Srephy Register
RESERVED Ethernet PHY Module Software Reset 0x0 = Ethernet PHY module is not reset. 0x1 = Ethernet PHY module is reset. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 314: Srcan Register
0x1 = CAN module 1 is reset. CAN Module 0 Software Reset 0x0 = CAN module 0 is not reset. 0x1 = CAN module 0 is reset. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 315: Sradc Register
0x1 = ADC module 1 is reset. ADC Module 0 Software Reset 0x0 = ADC module 0 is not reset. 0x1 = ADC module 0 is reset. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 316: Sracmp Register
Analog Comparator Module 0 Software Reset 0x0 = Analog comparator module is not reset. 0x1 = Analog comparator module is reset. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 317: Srpwm Register
RESERVED PWM Module 0 Software Reset 0x0 = PWM module 0 is not reset. 0x1 = PWM module 0 is reset. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 318: Srqei Register
RESERVED QEI Module 0 Software Reset 0x0 = QEI module 0 is not reset. 0x1 = QEI module 0 is reset. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 319: Sreeprom Register
Description 31-1 RESERVED EEPROM Module 0 Software Reset 0x0 = EEPROM module is not reset. 0x1 = EEPROM module is reset. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 320: Srccm Register
0x0 = The CRC, AES, DES, and SHA/MD5 modules are not reset. 0x1 = The CRC, AES, DES, and SHA/MD5 modules are reset. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 321: Srlcd Register
RESERVED LCD Module 0 Software Reset 0x0 = LCD module 0 is not reset. 0x1 = LCD module 0 is reset. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 322: Srowire Register
Reset Description 31-1 RESERVED 1-Wire Module Software Reset 0x0 = 1-Wire module is not reset. 0x1 = 1-Wire module is reset. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 323: Sremac Register
Ethernet Controller MAC Module 0 Software Reset 0x0 = Ethernet Controller MAC module 0 is not reset. 0x1 = Ethernet Controller MAC module 0 is reset. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 324: Rcgcwd Register
0x0 = Watchdog module 0 is disabled. 0x1 = Enable and provide a clock to Watchdog module 0 in run mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 325: Rcgctimer Register
0x0 = 16/32-bit general-purpose timer module 0 is disabled. 0x1 = Enable and provide a clock to 16/32-bit general-purpose timer module 0 in run mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 326: Rcgcgpio Register
0x0 = GPIO port K is disabled. 0x1 = Enable and provide a clock to GPIO port K in run mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 327 0x0 = GPIO port A is disabled. 0x1 = Enable and provide a clock to GPIO port A in run mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 328: Rcgcdma Register
µDMA Module Run Mode Clock Gating Control 0x0 = µDMA module is disabled. 0x1 = Enable and provide a clock to the µDMA module in run mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 329: Rcgcepi Register
EPI Module Run Mode Clock Gating Control 0x0 = EPI module is disabled. 0x1 = Enable and provide a clock to the EPI module in run mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 330: Rcgchib Register
Hibernation Module Run Mode Clock Gating Control 0x0 = Hibernation module is disabled. 0x1 = Enable and provide a clock to the Hibernation module in run mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 331: Rcgcuart Register
0x0 = UART module 0 is disabled. 0x1 = Enable and provide a clock to UART module 0 in run mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 332: Rcgcssi Register
0x0 = SSI module 0 is disabled. 0x1 = Enable and provide a clock to SSI module 0 in run mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 333: Rcgci2C Register
0x0 = I2C module 1 is disabled. 0x1 = Enable and provide a clock to I2C module 1 in run mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 334: Rcgci2C Register Field Descriptions
0x0 = I2C module 0 is disabled. 0x1 = Enable and provide a clock to I2C module 0 in run mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 335: Rcgcusb Register
USB Module Run Mode Clock Gating Control 0x0 = USB module is disabled. 0x1 = Enable and provide a clock to the USB module in run mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 336: Rcgcephy Register
Ethernet PHY Module Run Mode Clock Gating Control 0x0 = PHY module is disabled. 0x1 = Enable and provide a clock to the PHY module in run mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 337: Rcgccan Register
0x0 = CAN module 0 is disabled. 0x1 = Enable and provide a clock to CAN module 0 in run mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 338: Rcgcadc Register
0x0 = ADC module 0 is disabled. 0x1 = Enable and provide a clock to ADC module 0 in run mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 339: Rcgcacmp Register
0x0 = Analog comparator module is disabled. 0x1 = Enable and provide a clock to the analog comparator module in run mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 340: Rcgcpwm Register
0x0 = PWM module 0 is disabled. 0x1 = Enable and provide a clock to PWM module 0 in run mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 341: Rcgcqei Register
0x0 = QEI module 0 is disabled. 0x1 = Enable and provide a clock to QEI module 0 in run mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 342: Rcgceeprom Register
EEPROM Module 0 Run Mode Clock Gating Control 0x0 = EEPROM module is disabled. 0x1 = Enable and provide a clock to the EEPROM module in run mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 343: Rcgcccm Register
0x0 = The CRC, AES, DES, and SHA/MD 5 modules are disabled. 0x1 = Enable and provide a clock to the CRC, AES, DES, and SHA/MD5 modules in run mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 344: Rcgclcd Register
0x0 = LCD Controller module 0 is disabled. 0x1 = Enable and provide a clock to LCD Controller module 0 in run mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 345: Rcgcowire Register
0x0 = 1-Wire module 0 is disabled. 0x1 = Enable and provide a clock to 1-Wire module 0 in run mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 346: Rcgcemac Register
0x0 = Ethernet MAC module 0 is disabled. 0x1 = Enable and provide a clock to Ethernet MAC module 0 in run mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 347: Scgcwd Register
0x0 = Watchdog module 0 is disabled in sleep mode. 0x1 = Enable and provide a clock to Watchdog module 0 in sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 348: Scgctimer Register
0x0 = 16/32-bit general-purpose timer module 3 is disabled in sleep mode. 0x1 = Enable and provide a clock to 16/32-bit general-purpose timer module 3 in sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 349: Scgctimer Register Field Descriptions
0x0 = 16/32-bit general-purpose timer module 0 is disabled in sleep mode. 0x1 = Enable and provide a clock to 16/32-bit general-purpose timer module 0 in sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 350: Scgcgpio Register
0x0 = GPIO port M is disabled in sleep mode. 0x1 = Enable and provide a clock to GPIO port M in sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 351 0x0 = GPIO port A is disabled in sleep mode. 0x1 = Enable and provide a clock to GPIO port A in sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 352: Scgcdma Register
0x0 = µDMA module is disabled in sleep mode. 0x1 = Enable and provide a clock to the µDMA module in sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 353: Scgcepi Register
0x0 = EPI module is disabled in sleep mode. 0x1 = Enable and provide a clock to the EPI module in sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 354: Scgchib Register
0x0 = Hibernation module is disabled in sleep mode. 0x1 = Enable and provide a clock to the Hibernation module in sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 355: Scgcuart Register
0x0 = UART module 0 is disabled in sleep mode. 0x1 = Enable and provide a clock to UART module 0 in sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 356: Scgcssi Register
0x0 = SSI module 0 is disabled in sleep mode. 0x1 = Enable and provide a clock to SSI module 0 in sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 357: Scgci2C Register
0x0 = I2C module 1 is disabled in sleep mode. 0x1 = Enable and provide a clock to I2C module 1 in sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 358: Scgci2C Register Field Descriptions
0x0 = I2C module 0 is disabled in sleep mode. 0x1 = Enable and provide a clock to I2C module 0 in sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 359: Scgcusb Register
0x0 = USB module is disabled in sleep mode. 0x1 = Enable and provide a clock to the USB module in sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 360: Scgcephy Register
0x0 = PHY module is disabled in sleep mode. 0x1 = Enable and provide a clock to the PHY module in sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 361: Scgccan Register
0x0 = CAN module 0 is disabled in sleep mode. 0x1 = Enable and provide a clock to CAN module 0 in sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 362: Scgcadc Register
0x0 = ADC module 0 is disabled in sleep mode. 0x1 = Enable and provide a clock to ADC module 0 in sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 363: Scgcacmp Register
0x0 = Analog comparator module is disabled in sleep mode. 0x1 = Enable and provide a clock to the analog comparator module in sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 364: Scgcpwm Register
0x0 = PWM module 0 is disabled in sleep mode. 0x1 = Enable and provide a clock to PWM module 0 in sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 365: Scgcqei Register
0x0 = QEI module 0 is disabled in sleep mode. 0x1 = Enable and provide a clock to QEI module 0 in sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 366: Scgceeprom Register
0x0 = EEPROM module is disabled in sleep mode. 0x1 = Enable and provide a clock to the EEPROM module in sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 367: Scgcccm Register
0x0 = The CRC, AES, DES, and SHA/MD5 modules are disabled in sleep mode. 0x1 = Enable and provide a clock to the CRC, AES, DES, and SHA/MD5 modules in sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 368: Scgclcd Register
0x0 = LCD Controller module 0 is disabled in sleep mode. 0x1 = Enable and provide a clock to LCD Controller module 0 in sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 369: Scgcowire Register
0x0 = 1-Wire module 0 is disabled in sleep mode. 0x1 = Enable and provide a clock to 1-Wire module 0 in sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 370: Scgcemac Register
0x0 = Ethernet MAC module 0 is disabled in sleep mode. 0x1 = Enable and provide a clock to Ethernet MAC module 0 in sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 371: Dcgcwd Register
0x0 = Watchdog module 0 is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to Watchdog module 0 in deep- sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 372: Dcgctimer Register
0x0 = 16/32-bit general-purpose timer module 3 is disabled in deep- sleep mode. 0x1 = Enable and provide a clock to 16/32-bit general-purpose timer module 3 in deep-sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 373: Dcgctimer Register Field Descriptions
0x0 = 16/32-bit general-purpose timer module 0 is disabled in deep- sleep mode. 0x1 = Enable and provide a clock to 16/32-bit general-purpose timer module 0 in deep-sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 374: Dcgcgpio Register
0x0 = GPIO port M is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to GPIO port M in deep-sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 375: Dcgcgpio Register Field Descriptions
0x0 = GPIO port A is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to GPIO port A in deep-sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 376: Dcgcdma Register
0x0 = µDMA module is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to the µDMA module in deep-sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 377: Dcgcepi Register
0x0 = EPI module is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to the EPI module in deep-sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 378: Dcgchib Register
0x0 = Hibernation module is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to the Hibernation module in deep- sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 379: Dcgcuart Register
0x0 = UART module 1 is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to UART module 1 in deep-sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 380 0x0 = UART module 0 is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to UART module 0 in deep-sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 381: Dcgcssi Register
0x0 = SSI module 0 is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to SSI module 0 in deep-sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 382: Dcgci2C Register
0x0 = I2C module 3 is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to I2C module 3 in deep-sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 383: Dcgci2C Register Field Descriptions
0x0 = I2C module 0 is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to I2C module 0 in deep-sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 384: Dcgcusb Register
0x0 = USB module is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to the USB module in deep-sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 385: Dcgcephy Register
0x0 = PHY module is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to the PHY module in deep-sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 386: Dcgccan Register
0x0 = CAN module 0 is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to CAN module 0 in deep-sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 387: Dcgcadc Register
0x0 = ADC module 0 is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to ADC module 0 in deep-sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 388: Dcgcacmp Register
0x0 = Analog comparator module is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to the analog comparator module in deep-sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 389: Dcgcpwm Register
0x0 = PWM module 0 is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to PWM module 0 in deep-sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 390: Dcgcqei Register
0x0 = QEI module 0 is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to QEI module 0 in deep-sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 391: Dcgceeprom Register
0x0 = EEPROM module is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to the EEPROM module in deep- sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 392: Dcgcccm Register
0x0 = The CRC, AES, DES, and SHA/MD5 modules are disabled in deep-sleep mode. 0x1 = Enable and provide a clock to the CRC, AES, DES, and SHA/MD5 modules in deep-sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 393: Dcgclcd Register
0x0 = LCD controller module 0 is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to LCD controller module 0 in deep-sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 394: Dcgcowire Register
0x0 = 1-Wire module 0 is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to 1-Wire module 0 in deep-sleep mode. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 395: Dcgcemac Register
0x0 = Ethernet MAC module 0 is disabled in deep-sleep mode. 0x1 = Enable and provide a clock to Ethernet MAC module 0 in deep-sleep mode. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 396: Pcwd Register
Figure 4-154 and described in Table 4-162. Return to Summary Table. Figure 4-154. PCWD Register RESERVED R-0x0 RESERVED R-0x0 R/W- R/W- System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 397: Pcwd Register Field Descriptions
0x1 = Watchdog Timer 0 module is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 398: Pctimer Register
4-164. Return to Summary Table. Figure 4-155. PCTIMER Register RESERVED R-0x0 RESERVED R-0x0 R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 399: Pctimer Register Field Descriptions
0x1 = Timer 1 module is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 400 0x1 = Timer 0 module is powered but does not receive a clock. In this case, the module is inactive. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 401: Pcgpio Register
Figure 4-156. PCGPIO Register RESERVED R-0x0 R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 402: Pcgpio Register Field Descriptions
0x1 = GPIO port M is powered but does not receive a clock. In this case, the module is inactive. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 403 0x1 = GPIO port E is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 404 0x1 = GPIO port A is powered but does not receive a clock. In this case, the module is inactive. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 405: Pcdma Register
PCDMA is shown in Figure 4-157 and described in Table 4-168. Return to Summary Table. Figure 4-157. PCDMA Register RESERVED R-0x0 RESERVED R-0x0 R/W- SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 406: Pcdma Register Field Descriptions
0x1 = The µDMA module is powered but does not receive a clock. In this case, the module is inactive. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 407: Pcepi Register
PCEPI is shown in Figure 4-158 and described in Table 4-170. Return to Summary Table. Figure 4-158. PCEPI Register RESERVED R-0x0 RESERVED R-0x0 R/W- SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 408: Pcepi Register Field Descriptions
0x1 = The EPI module is powered but does not receive a clock. In this case, the module is inactive. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 409: Pchib Register
PCHIB is shown in Figure 4-159 and described in Table 4-172. Return to Summary Table. Figure 4-159. PCHIB Register RESERVED R-0x0 RESERVED R-0x0 R/W- SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 410: Pchib Register Field Descriptions
0x1 = The HIB module is powered but does not receive a clock. In this case, the module is inactive. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 411: Pcuart Register
4-174. Return to Summary Table. Figure 4-160. PCUART Register RESERVED R-0x0 RESERVED R-0x0 R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 412: Pcuart Register Field Descriptions
0x1 = The UART module 1 is powered but does not receive a clock. In this case, the module is inactive. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 413 0x1 = The UART module 0 is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 414: Pcssi Register
Table 4-176. Return to Summary Table. Figure 4-161. PCSSI Register RESERVED R-0x0 RESERVED R-0x0 R/W- R/W- R/W- R/W- System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 415: Pcssi Register Field Descriptions
0x1 = The SSI module 0 is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 416: Pci2C Register
Return to Summary Table. Figure 4-162. PCI2C Register RESERVED R-0x0 RESERVED R-0x0 R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 417: Pci2C Register Field Descriptions
0x1 = The I2C module 3 is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 418 0x1 = The I2C module 0 is powered but does not receive a clock. In this case, the module is inactive. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 419: Pcusb Register
0x1 = The USB module is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 420: Pcephy Register
PCEPHY is shown in Figure 4-164 and described in Table 4-182. Return to Summary Table. Figure 4-164. PCEPHY Register RESERVED R-0x0 RESERVED R-0x0 R/W- System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 421: Pcephy Register Field Descriptions
0x1 = The EPHY module is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 422: Pccan Register
0x1 = The CAN module 1 is powered but does not receive a clock. In this case, the module is inactive. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 423 0x1 = The CAN module 0 is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 424: Pcadc Register
Figure 4-166 and described in Table 4-186. Return to Summary Table. Figure 4-166. PCADC Register RESERVED R-0x0 RESERVED R-0x0 R/W- R/W- System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 425: Pcadc Register Field Descriptions
0x1 = The ADC module 0 is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 426: Pcacmp Register
PCACMP is shown in Figure 4-167 and described in Table 4-188. Return to Summary Table. Figure 4-167. PCACMP Register RESERVED R-0x0 RESERVED R-0x0 R/W- System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 427: Pcacmp Register Field Descriptions
0x1 = The Analog Comparator module is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 428: Pcpwm Register
PCPWM is shown in Figure 4-168 and described in Table 4-190. Return to Summary Table. Figure 4-168. PCPWM Register RESERVED R-0x0 RESERVED R-0x0 R/W- System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 429: Pcpwm Register Field Descriptions
0x1 = The PWM module 0 is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 430: Pcqei Register
PCQEI is shown in Figure 4-169 and described in Table 4-192. Return to Summary Table. Figure 4-169. PCQEI Register RESERVED R-0x0 RESERVED R-0x0 R/W- System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 431: Pcqei Register Field Descriptions
0x1 = QEI module 0 is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 432: Pceeprom Register
PCEEPROM is shown in Figure 4-170 and described in Table 4-194. Return to Summary Table. Figure 4-170. PCEEPROM Register RESERVED R-0x0 RESERVED R-0x0 R/W- System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 433: Pceeprom Register Field Descriptions
0x1 = The EEPROM module is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 434: Pcccm Register
PCCCM is shown in Figure 4-171 and described in Table 4-196. Return to Summary Table. Figure 4-171. PCCCM Register RESERVED R-0x0 RESERVED R-0x0 R/W- System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 435: Pcccm Register Field Descriptions
0x1 = The CRC, AES, DES, and SHA/MD5 modules are powered, but do not receive a clock. In this case, the modules are inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 436: Pclcd Register
0x1 = LCD module 0 is powered but does not receive a clock. In this case, the module is inactive. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 437: Pcowire Register
PCOWIRE is shown in Figure 4-173 and described in Table 4-200. Return to Summary Table. Figure 4-173. PCOWIRE Register RESERVED R-0x0 RESERVED R-0x0 R/W- SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 438: Pcowire Register Field Descriptions
0x1 = The 1-Wire module is powered but does not receive a clock. In this case, the module is inactive. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 439: Pcemac Register
0x1 = Ethernet MAC module 0 is powered but does not receive a clock. In this case, the module is inactive. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 440: Prwd Register
0x0 = Watchdog module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = Watchdog module 0 is ready for access. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 441: Prtimer Register
0x1 = 16/32-bit timer module 2 is ready for access. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 442: Prtimer Register Field Descriptions
0x1 = 16/32-bit timer module 0 is ready for access. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 443: Prgpio Register
0x0 = GPIO port M is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = GPIO port M is ready for access. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 444: Prgpio Register Field Descriptions
0x0 = GPIO port A is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = GPIO port A is ready for access. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 445: Prdma Register
0x0 = The µDMA module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = The µDMA module is ready for access. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 446: Prepi Register
0x0 = The EPI module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = The EPI module is ready for access. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 447: Prhib Register
0x0 = The Hibernation module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = The Hibernation module is ready for access. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 448: Pruart Register
0x0 = UART module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = UART module 1 is ready for access. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 449 0x0 = UART module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = UART module 0 is ready for access. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 450: Prssi Register
0x0 = SSI module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = SSI module 0 is ready for access. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 451: Pri2C Register
0x0 = I2C module 3 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = I2C module 3 is ready for access. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 452: Pri2C Register Field Descriptions
0x0 = I2C module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = I2C module 0 is ready for access. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 453: Prusb Register
0x0 = The USB module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = The USB module is ready for access. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 454: Prephy Register
0x1 = The Ethernet PHY module is ready for access. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 455: Prcan Register
0x0 = CAN module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = CAN module 0 is ready for access. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 456: Pradc Register
0x0 = ADC module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = ADC module 0 is ready for access. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 457: Pracmp Register
0x1 = The analog comparator module is ready for access. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 458: Prpwm Register
0x0 = PWM module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = PWM module 0 is ready for access. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 459: Prqei Register
0x0 = QEI module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = QEI module 0 is ready for access. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 460: Preeprom Register
0x0 = The EEPROM module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = The EEPROM module is ready for access. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 461: Prccm Register
They are unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = The CRC, AES, DES, and SHA/MD modules are ready for access. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 462: Prlcd Register
0x1 = LCD Controller module 0 is ready for access. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 463: Prowire Register
0x0 = 1-Wire module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 0x1 = 1-Wire module 0 is ready for access. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 464: Premac Register
0x1 = Ethernet MAC module 0 is ready for access. System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 465: Uniqueidn Register
Type Reset Description Unique ID 31-0 The result of registers 0 to 3 concatenated defines the unique 128- bit device identifier. SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 466: Ccm Registers
Access Type Code Description Read Type Read Write Type Write Reset or Default Value Value after reset or the default value System Control SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 467: Ccmcgreq Register
0x1 = Request to gate the clock SHACFG SHA/MD5 Clock Gating Request 0x0 = Request to ungate clock gating 0x1 = Request to gate the clock SLAU723A – October 2017 – Revised October 2018 System Control Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 468 ........................... Topic Page ..................Functional Description ................System Exception Registers Processor Support and Exception Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 469 Interrupt Status (SYSEXCRIS) register. Interrupts are always cleared (for both the SYSEXCMIS and SYSEXCRIS registers) by writing 1 to the corresponding bit in the System Exception Interrupt Clear (SYSEXCIC) register. SLAU723A – October 2017 – Revised October 2018 Processor Support and Exception Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 470: System Exception Registers
Write Type Write 1 to clear Write Reset or Default Value Value after reset or the default value Processor Support and Exception Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 471: Sysexcris Register
Floating-Point Input Denormal Exception Raw Interrupt Status This bit is cleared by writing 1 to the IDCIC bit in the SYSEXCIC register. SLAU723A – October 2017 – Revised October 2018 Processor Support and Exception Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 472: Sysexcim Register
Floating-Point Invalid Operation Interrupt Mask FPDZCIM Floating-Point Divide By 0 Exception Interrupt Mask FPIDCIM Floating-Point Input Denormal Exception Interrupt Mask Processor Support and Exception Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 473: Sysexcmis Register
Floating-Point Input Denormal Exception Masked Interrupt Status This bit is cleared by writing 1 to the FPIDCIC bit in the SYSEXCIC register. SLAU723A – October 2017 – Revised October 2018 Processor Support and Exception Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 474: Sysexcic Register
Writing 1 to this bit clears the FPIDCRIS bit in the SYSEXCRIS register and the FPIDCMIS bit in the SYSEXCMIS register. Processor Support and Exception Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 475 ........................... Topic Page ..................... Introduction ....................Block Diagram ..................Functional Description ................Initialization and Configuration ....................HIB Registers SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 476 Sixteen 32-bit words of battery-backed memory to save state during hibernation • Programmable interrupts for: – RTC match – External wake – Low battery Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 477: Hibernation Module Block Diagram
The second mechanism controls the power to the microcontroller with a control signal (HIB) that signals an external voltage regulator to turn on or off. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 478: Hib Clock Source Configurations
, otherwise, the Hibernation module may draw power from the oscillator and not V during hibernation. See Figure 6-2 Figure 6-3. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 479: Using A Crystal As The Hibernation Clock Source With A Single Battery Source
Open drain Battery external wake up circuit Figure 6-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 480: Using A Dedicated Oscillator As The Hibernation Clock Source With Vdd3On Mode
GPIO retention is released when software writes a 0 to the RETCLR bit. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 481: Using A Regulator For Both
Hibernate mode when a low-battery is detected. The module can also be configured to generate an interrupt for the low-battery condition (see Section 6.3.13). SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 482 RTCWEN bit in the HIBCTL register. The processor can also be programmed to generate an interrupt to the interrupt controller by setting the RTCALT0 bit in the HIBIM register. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 483 0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC rate and down from 0x7FFF in order to speed up the RTC rate. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 484: Counter Behavior With A Trim Value Of 0X8002
This module is a submodule of the Hibernate module. 6.3.6.1 Tamper Block Diagram Figure 6-7 shows the Tamper block diagram. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 485: Tamper Block Diagram
STATE field in the HIB Tamper Status (HIBTPSTAT) register. In addition, the XOSCST and XOSCFAIL bits can be read for further details on the external oscillator source state. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 486: Tamper Pad With Glitch Filtering
The RTC seconds or calendar values of year, minutes, day of month, hours and seconds in the HIBTPLOG0, HIBTPLOG2, HIBTPLOG4, and HIBTPLOG6 registers Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 487 A cold POR occurs when both the V and V supplies are removed. Any other reset condition is ignored by the Hibernation module. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 488 The Hibernation module can be configured to wake from Hibernate mode if any of the following are enabled: • External WAKE • External RST • GPIO K[7:4] • Tamper TMPR[3:0] • Tamper XOSC failure Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 489 PINWEN bit in the HIBCTL register • RTCEN bit in the HIBCTL register The microcontroller wakes from hibernation when power is reapplied. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 490 3. Wait until the WC interrupt in the HIBMIS register has been triggered before performing any other operations with the Hibernation module. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 491 5. The hibernation sequence may be initiated by writing 0x4000.0152 to the HIBCTL register. Note that when using RESET, the user must enable VDD3ON mode and set the RETCLR bit in the HIBCTL register. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 492 NOTE: When tamper is enabled, the following HIBCTL register bits are locked and cannot be modified: • OSCSEL • OSCDRV • OSCBYP • VDD3ON • CLK32EN • RTCEN Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 493: Hib Registers
0x300 HIBCALCTL Hibernation Calendar Control Section 6.5.13 0x310 HIBCAL0 Hibernation Calendar 0 Section 6.5.14 0x314 HIBCAL1 Hibernation Calendar 1 Section 6.5.15 SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 494: Hib Access Type Codes
Read Type Read Write Type Write 1 to clear Write Reset or Default Value Value after reset or the default value Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 495: Hibrtcc Register
A read returns the 32-bit counter value, which represents the seconds elapsed since the RTC was enabled. This register is read-only. To change the value, use the HIBRTCLD register. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 496: Hibrtcm0 Register
0xFFFFFFFF RTC Match 0 A write loads the value into the RTC match register. A read returns the current match value. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 497: Hibrtcld Register
RTCLD RTC Load A write loads the current value into the RTC counter (RTCC). A read returns the 32-bit load value. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 498: Hibctl Register
R/W-0x1 R-0x0 R/W-0x0 R/W-0x0 R/W-0x0 VABORT CLK32EN RESERVED PINWEN RTCWEN RESERVED HIBREQ RTCEN R/W-0x0 R/W-0x0 R-0x0 R/W-0x0 R/W-0x0 R-0x0 R/W-0x0 R/W-0x0 Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 499: Hibctl Register Field Descriptions
0x1 = The internal 32.768-kHz Hibernation oscillator is disabled and powered down. This bit should be set when using a single-ended oscillator attached to XOSC0. RESERVED SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 500 This bit must be enabled to use the Hibernation module. 0x0 = The Hibernation module clock source is disabled. 0x1 = The Hibernation module clock source is enabled. RESERVED Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 501 0x0 = The Hibernation module RTC and calendar mode are disabled. 0x1 = The Hibernation module RTC and calendar mode are enabled. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 502: Hibim Register
0x1 = An interrupt is sent to the interrupt controller when the WC bit in the HIBRIS register is set. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 503 0x1 = An interrupt is sent to the interrupt controller when the RTCALT0 bit in the HIBRIS register is set. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 504: Hibris Register
0x0 = The WRC bit in the HIBCTL has not been set. 0x1 = The WRC bit in the HIBCTL has been set. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 505 Calendar function is enabled, this interrupt status indicates that one or more of the allowed fields in the HIBCAL0/1 register matches in the HIBCALM0/1 register.. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 506: Hibmis Register
0x0 = An external wake-up interrupt has not occurred or is masked. 0x1 = An unmasked interrupt was signaled due to a WAKE pin assertion. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 507 0x0 = An RTC or calendar match interrupt has not occurred or is masked. 0x1 = An unmasked interrupt was signaled due to an RTC or calendar match. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 508: Hibic Register
Writing a 1 to this bit clears the EXTW bit in the HIBRIS and HIBMIS registers. Reads return the raw interrupt status. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 509 The timer interrupt source cannot be cleared if the RTC value and the HIBRTCM0 register / RTCMSS field values are equal. The match interrupt takes priority over the interrupt clear. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 510: Hibrtct Register
0x7FFF up or down. Moving the value up slows down the RTC and moving the value down speeds up the RTC. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 511: Hibrtcss Register
This field contains the sub second RTC count and is read as RTCOSC clock units. For the 32. 768-kHz clock source, this would be in units of 1/32,768 seconds. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 512: Hibio Register
RST pin and/or GPIO wake-enabled pins.This bit must be cleared before issuing a hibernate request by setting the HIBREQ bit in the HIBCTL register. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 513: Hibdata Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R/W-X Table 6-15. HIBDATA Register Field Descriptions Field Type Reset Description 31-0 Hibernation Module NV Data SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 514: Hibcalctl Register
The RTC must be enabled by setting the RTCEN bit in the HIBCTL register to use this mode select. 0x0 = RTC Counter mode enabled. 0x1 = Calendar mode enabled Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 515: Hibcal0 Register
This field holds the seconds value in hexadecimal. Bits 5:0 correspond to hex values from 0x0 to 0x3b (0 to 59 seconds). SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 516: Hibcal1 Register
4:0 correspond to hex values from 0x1 to 1F (1 to 31 days). The value 0 is used to show an ignore match. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 517: Hibcalld0 Register
This field holds the seconds value in hexadecimal. Bits 5:0 correspond to hex values from 0x0 to 0x3B (0 to 59 seconds). SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 518: Hibcalld1 Register
4:0 correspond to hex values from 0x1 to 1F (1 to 31 days). The encoding 0x0 is RESERVED for the ignore match function. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 519: Hibcalm0 Register
5:0 correspond to hex values from 0x0 to 0x3b (0 to 59 seconds). To ignore the hours match, write this field to all 1s. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 520: Hibcalm1 Register
4:0 correspond to hex values from 0x1 to 1F (1 to 31 days). To disable match for the day of the month, the value 0x0 is used. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 521: Hiblock Register
Table 6-23. HIBLOCK Register Field Descriptions Field Type Reset Description 31-0 HIBLOCK Hibernate Lock A write of 0xA3359554 unlocks the HIBRCTL and Tamper registers. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 522: Hibtpctl Register
Writing a 1 to this bit clears the tamper event. The status of the clear is reflected in the STATE bit field. RESERVED Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 523 Once tamper is enabled, the following HIBCTL register bits are locked and cannot be modified:OSCSEL OSCDRV OSCBYP VDD3ON CLK32EN RTCEN 0x0 = Tamper module disabled. 0x1 = Tamper module Enabled. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 524: Hibtpstat Register
Write a 1 to this bit to clear it. 0x0 = External oscillator is valid. 0x1 = External oscillator has failed Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 525: Hibtpio Register
0x0 = Trigger on level low 0x1 = Trigger on level high TMPR3 Enable 0x0 = Detect disabled 0x1 = Detect enabled 23-20 RESERVED SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 526 0x0 = Trigger on level low 0x1 = Trigger on level high TMPR0 Enable 0x0 = Detect disabled 0x1 = Detect enabled Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 527: Hibtplog0 Register
The format of the calendar information is as follows: TIME[31:26]: Year (0-64) TIME[25:22]: Month TIME[21:17]: Day of month TIME[16:12]: Hours TIME[11:6]: Minutes TIME[5:0]: Seconds SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 528: Hibtplog1 Register
0x1 = A tamper event has been detected on TMPR[1] TRIG0 Status of TMPR[0] Trigger 0x0 = Default 0x1 = A tamper event has been detected on TMPR[0] Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 529: Hibpp Register
WAKENC Wake Pin Presence 0x0 = WAKE pin is present. 0x1 = WAKE pin is not part of the package pinout. SLAU723A – October 2017 – Revised October 2018 Hibernation Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 530: Hibcc Register
0x0 = RTCOSC is not available as a system clock source. 0x1 = RTCOSC is available for use as a system clock source. Hibernation Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 531 ........................... Topic Page ....................Block Diagram ..................Functional Description ....................Flash Registers ................... EEPROM Registers ..............System Control Memory Registers SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 532: Internal Memory Block Diagram
This section describes the functionality of the SRAM, ROM, flash, and EEPROM memories. NOTE: The µDMA has read-only access to flash (in run mode only). Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 533 NOTE: CRC and AES software programs are available for backward compatibility. A device that has enhanced CRC and AES integrated modules should use this hardware for best performance. Chapter 13 Chapter 9 for more information. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 534: Boot Configuration Flow
Is flash data = 0xFFFFFFFF at address 0x00000004? Proceed to Proceed to ROM bootloader application image Figure 7-2. Boot Configuration Flow Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 535: Flash Memory Configuration
0x00.000C 0x00.0008 0x00.0004 0x00.0000 256 KB Bank 1: 128-bit output 256 KB Bank 0: 128-bit output Figure 7-3. Flash Memory Configuration SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 536: Single 256-Bit Prefetch Buffer Set
When the buffers are configured as four, 256-bit buffers, they function as one set with one of the four buffers tagged as the LRU and the next to be used when an autofill or miss occurs. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 537: Four 256-Bit Prefetch Buffer Configuration
CPU with zero-wait-state delay. • EVENT D: Word 0 from the second fetch that occurred is sent to the CPU. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 538: Prefetch Fills From Flash
Prefetch buffer valid tags can be cleared by setting the CLRTV bit in the FLASHCONF register. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 539: Mirror Mode Function
(written) or erased. When bits are cleared, the corresponding block can not be changed. When a block is protected by clearing bits in both FMPPEn and FMPREn registers, execute-only protection can be achieved. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 540: Flash Memory Protection Policy Combinations
LDR offset is relative to the beginning of the pool. 2. Use a compiler that generates literal data from arithmetic instruction immediate data and subsequent computation. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 541 NOTE: The µDMA can only access flash in run mode (not available in low power modes). SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 542 32 FWBn registers, where bit[n] of FWBVAL corresponds to FWBn. The FWBn register has been updated if the corresponding bit in the FWBVAL register is set. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 543 See Table 7-3 for the list of nonvolatile registers. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 544: User-Programmable Flash Memory Resident Registers
Access protection per block • Lock protection option for the whole peripheral as well as per block using 32-bit to 96-bit unlock codes Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 545 EEPROM Bank Clock Edge (EBCE) and the EEPROM Wait States (EWS) in the Memory Timing Parameter Register 0 for main flash and EEPROM (MEMTIM0) register at System Control Module offset 0x0C0. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 546: Memtim0 Register Configuration And Frequency
Supervisor-only access mode also prevents access by the µDMA and Debugger. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 547 (SREEPROM) register, wait until WORKING bit in the EEPROM Done Status (EEDONE) register is clear, and then enable the debug mass erase by setting the ME bit in the EEPROM Debug Mass Erase (EEDBGME) register. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 548 All words can be written in a sweep with a total of more than 500000 sweeps which updates all words more than 500000 times. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 549: Master Memory Access Availability
Yes (read only, run- µDMA – mode only) Ethernet Module – – – – – – – – – – – SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 550: Flash Registers
Read Type Read Write Type Write 1 to clear Write Reset or Default Value Value after reset or the default value Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 551: Fma Register
Reset Description 31-20 RESERVED 19-0 OFFSET Address Offset Address offset in Flash memory where operation is performed, except for non-volatile registers. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 552: Fmd Register
DATA R/W-0x0 Table 7-9. FMD Register Field Descriptions Field Type Reset Description 31-0 DATA Data Value Data value for write operation. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 553: Fmc Register
0x1 = Set this bit to commit (write) the register value to a Flash- memory-resident register.When read, a 1 indicates that the previous commit access is not complete. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 554 Flash memory location specified by the contents of the FMA register.When read, a 1 indicates that the write update access is not complete. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 555: Fcris Register
0x1 = An interrupt is pending because a bit that was previously programmed as a 0 is now being requested to be programmed as a SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 556 0x1 = A program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 557: Fcim Register
0x0 = The ERIS interrupt is suppressed and not sent to the interrupt controller. 0x1 = An interrupt is sent to the interrupt controller when the ERIS bit is set. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 558 0x0 = The ARIS interrupt is suppressed and not sent to the interrupt controller. 0x1 = An interrupt is sent to the interrupt controller when the ARIS bit is set. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 559: Fcmisc Register
0x1 = When read, a 1 indicates that an unmasked interrupt was signaled.Writing a 1 to this bit clears VOLTMISC and also the VOLTRIS bit in the FCRIS register (see ). RESERVED SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 560 FMPPEn registers.Writing a 1 to this bit clears AMISC and also the ARIS bit in the FCRIS register (see ). Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 561: Fmc2 Register
FMA register.When read, a 1 indicates that the previous buffered Flash memory write access is not complete. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 562: Fwbval Register
0x1 = The corresponding FWBn register has been updated since the last buffer write operation and is ready to be written to Flash memory. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 563: Flpekey Register
When a value other than all 1s or all 0s, this 16-bit value is used as the "match" for the upper 16-bits of the register FMC and FMC2 keys. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 564: Fwbn Register
Table 7-17. FWBn Register Field Descriptions Field Type Reset Description 31-0 DATA Data Data to be written into the Flash memory. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 565: Flashpp Register
0x4 = 16KB 15-0 SIZE 0x1FF Flash Size Indicates the size of the on-chip Flash memory 0x01FF = 1024KB of Flash SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 566: Ssize Register
Reset Description 31-16 RESERVED 15-0 SIZE 0x3FF SRAM Size Indicates the size of the on-chip SRAM. 0x03FF = 256KB of SRAM Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 567: Flashconf Register
0x1 = Force prefetch buffers to be enabled. FPFOFF Force Prefetch Off 0x0 = No effect 0x1 = Force prefetch buffers to be disabled. 15-0 RESERVED SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 568: Romswmap Register
0x1 = Region available to core SW0EN ROM SW Region 0 Availability 0x0 = RESERVED 0x1 = Region available to core Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 569: Flashdmasz Register
Note that the DFA bit must be set in the FLASHPP register before this value can be programmed. Size of region is defined as 2 × (SIZE + 1) KB. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 570: Flashdmast Register
Contains the starting address of the flash region accessible by µDMA if the FLASHPP register DFA bit is set 10-0 RESERVED Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 571: Eeprom Registers
Access Type Code Description Read Type Read Write Type Write Reset or Default Value Value after reset or the default value SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 572: Eesize Register
WORDCNT 0x600 Number of 32-Bit Words This value encoded in this field describes the number of 32-bit words in the EEPROM. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 573: Eeblock Register
Attempts to write this field larger than the maximum number of blocks or to a locked block causes this field to be configured to 0. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 574: Eeoffset Register
The offset is automatically incremented by the EERDWRINC register, with wrap around within the block, which means the offset is incremented from 15 back to 0. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 575: Eerdwr Register
If protection and access rules do not permit reads, all 1s are returned. If protection and access rules do not permit writes, the write fails and the EEDONE register indicates failure. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 576: Eerdwrinc Register
Regardless of error, the OFFSET field in the EEOFFSET register is incremented by 1, and the value wraps around if the last word is reached. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 577: Eedone Register
SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 578 RESERVED WORKING EEPROM Working 0x0 = The EEPROM is not working. 0x1 = The EEPROM is performing the requested operation. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 579: Eesupp Register
0x1 = Erasing failed to complete. If the failed erase is due to the erase of a main buffer, the copy is performed after the erase completes successfully. RESERVED SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 580: Eeunlock Register
It can be locked again by writing 0xFFFFFFFF to this register. 0x0 = The EEPROM is locked. 0x1 = The EEPROM is unlocked. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 581: Eeprot Register
0x2 = Without password: the block is readable, not writable.With password: the block is readable only when unlocked, but is not writable under any conditions. 0x3 = Reserved SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 582: Eepass0 To Eepass2 Registers
If an attempt is made to write to this register when it reads as 0x1, the write is ignored and the NOPERM bit in the EEDONE register is set. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 583: Eeint Register
1 to 0 or an error occurs. The EEDONE register provides status after a write to an offset location as well as a write to the password and protection bits. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 584: Eehide0 Register
OFFSET field to a hidden block, the EEBLOCK register is cleared.Any attempt to clear a bit in this register that is set is ignored. RESERVED Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 585: Eehide1 Register
OFFSET field to a hidden block, the EEBLOCK register is cleared. Any attempt to clear a bit in this register that is set is ignored. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 586: Eehide2 Register
OFFSET field to a hidden block, the EEBLOCK register is cleared.Any attempt to clear a bit in this register that is set is ignored. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 587: Eedbgme Register
0x1 = When written as a 1, the EEPROM is mass erased. This bit continues to read as 1 until the EEPROM is fully erased. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 588: Eeprompp Register
0x001F = 2KB of EEPROM 0x003F = 3KB of EEPROM 0x007F = 4KB of EEPROM 0x00FF = 5KB of EEPROM 0x01FF = 6KB of EEPROM Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 589: System Control Memory Registers
Access Type Code Description Read Type Read Write Type Write Reset or Default Value Value after reset or the default value SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 590: Rvp Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R-0x0101FFF0 Table 7-44. RVP Register Field Descriptions Field Type Reset Description 31-0 0x0101FFF Reset Vector Pointer Address Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 591: Boot Configuration Flow
Is flash data = 0xFFFFFFFF at address 0x00000004? Proceed to Proceed to ROM bootloader application image Figure 7-42. Boot Configuration Flow SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 592: Bootcfg Register
0x2 = Port C 0x3 = Port D 0x4 = Port E 0x5 = Port F 0x6 = Port G 0x7 = Port H Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 593: Bootcfg Register Field Descriptions
DBG0 Debug Control 0 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 594: User_Regn Register
Contains the user data value. This field is initialized to all 1s and once committed, retains its value through power-on reset. Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 595 FMPRE7 : 449 to 512KB • FMPRE8 : 513 to 576KB • FMPRE9 : 577 to 640KB • FMPRE10 : 641 to 704KB SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 596: Fmpren Register
16KB read-protected sector. The policies may be combined as shown in the table "Flash Protection Policy Combinations". Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 597 FMPPE7 : 449 to 512KB • FMPPE8 : 513 to 576KB • FMPPE9 : 577 to 640KB • FMPPE10 : 641 to 704KB SLAU723A – October 2017 – Revised October 2018 Internal Memory Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 598: Fmppen Register
Every eighth bit programs an 16KB flash sector to be execute only. The policies may be combined as shown in . Internal Memory SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 599 Block Diagram ..................Functional Description ................Initialization and Configuration ............µDMA Channel Control Structure Registers ....................µDMA Registers SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 600 Interrupt on transfer completion with a separate interrupt per channel Block Diagram Figure 8-1 shows the µDMA block diagram. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 601: Μdma Block Diagram
µDMA service request. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 602: Request Type Support
TX FIFO level (fixed at 4) SSI RX RX FIFO not empty RX FIFO level (fixed at 4) Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 603 SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 604: Control Structure Memory Map
At the end of a transfer, the µDMA controller updates the control word to set the mode to Stop. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 605 For an example showing operation in Ping-Pong mode, see Figure 8-2. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 606: Example Of Ping-Pong Μdma Transaction
Process data in BUFFER B Unused x Reload alternate structure Figure 8-2. Example of Ping-Pong µDMA Transaction Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 607 B operation with the alternate control structure. The process is repeated for task C. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 608: Memory Scatter-Gather, Setup And Configuration
4. The SRC and DST pointers in the task list must point to the last location in the corresponding buffer. Figure 8-3. Memory Scatter-Gather, Setup and Configuration Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 609: Memory Scatter-Gather, Μdma Copy Sequence
µDMA controller copies data from the source buffer FKDQQHO¶V DOWHUQDWH FRQWURO VWUXFWXUH. C to the destination buffer. Figure 8-4. Memory Scatter-Gather, µDMA Copy Sequence SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 610: Peripheral Scatter-Gather, Setup And Configuration
µDMA controller. Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 611: Peripheral Scatter-Gather, Μdma Copy Sequence
C to the peripheral structure. data register. Figure 8-6. Peripheral Scatter-Gather, µDMA Copy Sequence SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 612: Μdma Read Example: 8-Bit Peripheral
If two additional trigger peripheral µDMA requests are generated before the completion of the first, the third request is lost. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 613: Μdma Interrupt Assignments
3. Program the location of the channel control table by writing the base address of the table to the DMA Channel Control Base Pointer (DMACTLBASE) register. The base address must be aligned on a 1024- byte boundary. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 614: Channel Control Structure Offsets For Channel
Use Auto-request transfer mode The value of this bit must be 1 (privileged) for AES, DES, or SHA accesses. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 615: Channel Control Structure Offsets For Channel
2. Program the destination end pointer at offset 0x074 to the address of the peripheral's transmit FIFO register. The control word at offset 0x078 must be programmed according to Table 8-9. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 616: Channel Control Word Configuration For Peripheral Transmit Example
3. Set bit 8 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the µDMA Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 617: Primary And Alternate Channel Control Structure Offsets For Channel
Privileged access protection for destination data writes reserved 20:19 Reserved SRCPROT0 Privileged access protection for source data reads ARBSIZE 17:14 Arbitrates after 8 transfers SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 618 Channel assignments for each µDMA channel can be changed using the DMACHMAPn registers. Each 4- bit field represents a µDMA channel. For channel assignments, see the device-specific data sheet. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 619 UART1 RX channel 22 priority needs to be lowered before channel 8 UART1 RX can be accessed by the µDMA. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 620: Μdma Channel Control Structure Registers
Description Read Type Read Write Type Write Reset or Default Value Value after reset or the default value Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 621: Dmasrcendp Register
DMACHCTL register is 0x3), then this field points at the source location itself (such as a peripheral data register). SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 622: Dmadstendp Register
DMACHCTL register is 0x3), then this field points at the destination location itself (such as a peripheral data register). Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 623: Dmachctl Register
0x3 = No increment Address remains set to the value of the Source Address End Pointer (DMASRCENDP) for the channel SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 624 If this bit is set, then the controller uses a burst transfer to complete the last transfer. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 625: Xfermode Bit Field Values
This value must be used in the alternate channel control data structure when the µDMA controller operates Scatter-Gather in Peripheral Scatter-Gather mode. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 626: Μdma Registers
Access Type Code Description Read Type Read Write Type Write 1 to clear Write Reset or Default Value Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 627 Table 8-19. UDMA Access Type Codes (continued) Access Type Code Description Value after reset or the default value SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 628: Dmastat Register
MASTEN Master Enable Status 0x0 = The µDMA controller is disabled. 0x1 = The µDMA controller is enabled. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 629: Dmacfg Register
Description 31-1 RESERVED MASTEN Controller Master Enable 0x0 = Disables the µDMA controller. 0x1 = Enables µDMA controller. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 630: Dmactlbase Register
This field contains the pointer to the base address of the channel control table. The base address must be 1024-byte aligned. RESERVED Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 631: Dmaaltbase Register
ADDR 0x200 Alternate Channel Address Pointer This field provides the base address of the alternate channel control structures. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 632: Dmawaitstat Register
0x0 = The corresponding channel is not waiting on a request. 0x1 = The corresponding channel is waiting on a request. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 633: Dmaswreq Register
These bits are automatically cleared when the software request has been completed. 0x0 = No request generated. 0x1 = Generate a software request for the corresponding channel. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 634: Dmauseburstset Register
0x0 = µDMA channel [n] responds to single or burst requests. 0x1 = µDMA channel [n] responds only to burst requests. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 635: Dmauseburstclr Register
0x1 = Setting a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register meaning that µDMA channel [n] responds to single and burst requests. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 636: Dmareqmaskset Register
0x1 = The peripheral associated with channel [n] is not able to request µDMA transfers. Channel [n] may be used for software- initiated transfers. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 637: Dmareqmaskclr Register
0x1 = Setting a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register meaning that the peripheral associated with channel [n] is enabled to request µDMA transfers. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 638: Dmaenaset Register
DMAENACLR register or when the end of a µDMA transfer occurs. 0x0 = µDMA Channel [n] is disabled. 0x1 = µDMA Channel [n] is enabled. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 639: Dmaenaclr Register
0x1 = Setting a bit clears the corresponding SET[n] bit in the DMAENASET register meaning that channel [n] is disabled for µDMA transfers. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 640: Dmaaltset Register
0x0 = µDMA channel [n] is using the primary control structure. 0x1 = µDMA channel [n] is using the alternate control structure. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 641: Dmaaltclr Register
0x1 = Setting a bit clears the corresponding SET[n] bit in the DMAALTSET register meaning that channel [n] is using the primary control structure. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 642: Dmaprioset Register
0x0 = µDMA channel [n] is using the default priority level. 0x1 = µDMA channel [n] is using a high priority level. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 643: Dmaprioclr Register
0x1 = Setting a bit clears the corresponding SET[n] bit in the DMAPRIOSET register meaning that channel [n] is using the default priority level. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 644: Dmaerrclr Register
This bit is cleared by writing a 1 to it. 0x0 = No bus error is pending. 0x1 = A bus error is pending. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 645: Dmachmap0 Register
µDMA Channel 1 Source Select See for channel assignments. CH0SEL µDMA Channel 0 Source Select See for channel assignments. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 646: Dmachmap1 Register
µDMA Channel 9 Source Select See for channel assignments. CH8SEL µDMA Channel 8 Source Select See for channel assignments. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 647: Dmachmap2 Register
µDMA Channel 17 Source Select See for channel assignments. CH16SEL µDMA Channel 16 Source Select See for channel assignments. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 648: Dmachmap3 Register
µDMA Channel 25 Source Select See for channel assignments. CH24SEL µDMA Channel 24 Source Select See for channel assignments. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 649: Dmaperiphid4 Register
RESERVED PID4 µDMA Peripheral ID Register Can be used by software to identify the presence of this peripheral. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 650: Dmaperiphid0 Register
0x30 µDMA Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 651: Dmaperiphid1 Register
0xB2 µDMA Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 652: Dmaperiphid2 Register
PID2 µDMA Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 653: Dmaperiphid3 Register
PID3 µDMA Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 654: Dmapcellid0 Register
Type Reset Description 31-8 RESERVED CID0 µDMA PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 655: Dmapcellid1 Register
Reset Description 31-8 RESERVED CID1 0xF0 µDMA PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 656: Dmapcellid2 Register
Type Reset Description 31-8 RESERVED CID2 µDMA PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. Micro Direct Memory Access (µDMA) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 657: Dmapcellid3 Register
Reset Description 31-8 RESERVED CID3 0xB1 µDMA PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. SLAU723A – October 2017 – Revised October 2018 Micro Direct Memory Access (µDMA) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 658 AES Functional Description ................AES Performance Information ............... AES Module Programming Guide ....................AES Registers ..................AES µDMA Registers Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 659 The following sections describe the features of the AES Module. 9.2.1 AES Block Diagram Figure 9-1 shows the AES block diagram. A single-core dual-interface architecture is used. SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 660: Aes Block Diagram
128, 192, and 256 bits, which require 10, 12, and 14 rounds, respectively, or 32, 38, and 44 clock cycles, respectively, because {number of clock cycles} = 2 + 3 × {number of rounds}. Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 661 AES algorithm is the S-Box. The S-Box provides a unique 8-bit output for each 8-bit input. This implementation of the AES encryption core has a 64-bit data path. SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 662 – Nr = 14 when Nk = 8 (256-bit key) Table 9-1 lists the combinations of keys, blocks, and rounds. Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 663: Key-Block Round Combinations
For decryption, the cryptographic core operates in reverse: the decryption data path is used for data processing, whereas encryption uses the encryption data path. SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 664: Aes - Ecb Feedback Mode
(CTR/ICM) mode of operation. This operation encrypts the IV. The output of the cryptographic core (encrypted IV) is XORed with the data, therefore creating the output result. Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 665: Aes Encryption With Ctr/Icm Mode
Temporary Buffer Ouput Buffer Ouput Buffer (cipher text) (plain text) Encryption Decryption Figure 9-5. AES – CFB Feedback Mode SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 666: Aes - F8 Mode
XORed with the IV; the output of the cryptographic core is XORed with the same IV. For decryption, the cryptographic core operates in reverse, but the XOR operations are the same. Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 667: Aes - Xts Operation
Key in AES Core Key Register (encrypt) data_out Authentication Result (TAG) Figure 9-8. AES – F9 Operation SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 668: Aes - Cbc-Mac Authentication Mode
Key in AES Core Key Register (encrypt) data_out Authentication Result (TAG Figure 9-9. AES – CBC-MAC Authentication Mode Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 669: Aes - Gcm Operation
(encrypt) data_out Temporary Buffer Ouput Buffer (cipher text) Authentication Authentication Key Result Figure 9-10. AES – GCM Operation SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 670: Aes - Ccm Operation
128- bit length vector and finally encrypt the authentication result. Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 671: Interrupts And Events
AES_IRQSTATUS [2]: DATA_OUT Data output interrupt AES_IRQSTATUS [1]: DATA_IN Data input interrupt AES_IRQSTATUS [0]: CONTEXT_IN Context input interrupt SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 672: Aes Module Performance (Input/Output Block Size = 128)
(complete GCM mode), this number needs to be doubled. If Y0-encrypted is not calculated (forced to zero, such that the hash result is not encrypted) this number is zero. Input Only Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 673: Aes Module Packet Mode Switch Overhead
Numbers for regular CCM mode. Dependent on the AAD length it is possible that one additional encryption needs to be done to finalize the AAD authentication; if the additional operation is required, this number needs to be doubled. SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 674 (AES_AUTH_LENGTH) register at offset 0x05C. 3. Select the IV counter by programming the CTR_WIDTH field in the AES_CTRL register. Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 675 2. Select counter width by programming the CTR_WIDTH in the AES_CTRL register. 3. Load the AES Initialization Vector Input n (AES_IV_IN_n) registers at offset 0x040 to 0x04C. SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 676: Aes Polling Mode
The application can use software interrupts to control the flow of Context In, Context Out, Data In, and Data Out requests. To enable these interrupts: Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 677 • AES_IRQSTATUS • AES_KEY1_n • AES_KEY2_n • AES_IV_IN_n • AES_DATA_IN_n • AES_TAG_OUT_n • AES_IRQENABLE SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 678: Aes Interrupt Service
Clear interrupt status AES_IRQSTATUS [3:0] = 0x0 Enable interrupts AES_IRQENABLE [3:0] = 0xF Figure 9-13. AES Interrupt Service Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 679: Aes Registers
Table 9-6. AES Access Type Codes Access Type Code Description Read Type Read Write Type SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 680 Code Description Write 1 to clear Write Reset or Default Value Value after reset or the default value Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 681: Aes_Keyn_N Register
Field Type Reset Description 31-0 Key Data. This register contains the 32-bit key data for the AES module. SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 682: Aes_Iv_In_N Register
The least significant word (LSW) is represented in register AES_IV_IN_0 and the most significant word is stored in AES_IV_IN_3 Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 683: Aes_Ctrl Register
The AES Engine always returns a 128-bit authentication field, of which the M least significant bytes are valid. All values are supported. SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 684 This is a counter mode with a 16-bit wide counter. 0x0 = AES-ICM mode is not enabled. 0x1 = AES-ICM mode is enabled. Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 685 0x0 = No AES output block is available. 0x1 = An AES output block is available for the host to retrieve. SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 686: Aes_C_Length_N Register
Reset Description 31-0 LENGTH Data Length. This field stores the cryptographic data length in bytes for all modes. Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 687: Aes_Auth_Length Register
Authentication Data Length. This field stores the authentication data length in bytes for combined modes (GCM or CCM). SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 688: Aes_Data_In_N Register
Table 9-13. AES_DATA_IN_n Register Field Descriptions Field Type Reset Description 31-0 DATA Secure Data R/W Plaintext/Ciphertext. This field holds the plaintext/ciphertext data. Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 689: Aes_Tag_Out_N Register
Table 9-14. AES_TAG_OUT_n Register Field Descriptions Field Type Reset Description 31-0 HASH Hash Result. This field holds the hash result. SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 690: Aes_Revision Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 REVISION R-0x41 Table 9-15. AES_REVISION Register Field Descriptions Field Type Reset Description 31-0 REVISION 0x41 Revision number Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 691: Aes_Sysconfig Register
0x0 = DMA disabled for context output request. 0x1 = DMA enabled for context output request. SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 692: Aes_Sysconfig Register Field Descriptions
0x1 = DMA enabled for data input request. RESERVED SOFTRESET Soft reset 0x0 = No operation 0x1 = Start soft reset sequence RESERVED Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 693: Aes_Sysstatus Register
Description 31-1 RESERVED RESETDONE Reset Done 0x0 = Reset is not complete. 0x1 = Reset is has completed. SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 694: Aes_Irqstatus Register
0x0 = The context in interrupt is not active. 0x1 = The context in interrupt is active and the interrupt output has been triggered. Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 695: Aes_Irqenable Register
Context In Interrupt Enable 0x0 = The context in interrupt is disabled. 0x1 = The context in interrupt is enabled. SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 696: Aes_Dirtybits Register
0x0 = No AES registers have been read. 0x1 = Indicates when any of the AES_x registers have been read (except for the AES_DIRTYBITS register). Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 697: Aes Μdma Registers
Write Type Write 1 to clear Write Reset or Default Value Value after reset or the default value SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 698: Aes_Dmaim Register
0x0 = The CIN interrupt is suppressed and not sent to the interrupt controller. 0x1 = The CIN interrupt is sent to the interrupt controller. Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 699: Aes_Dmaris Register
0x1 = The µDMA has completed a context write to the internal register and an interrupt has been triggered and is pending. SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 700: Aes_Dmamis Register
Context In DMA Done Raw Interrupt Status 0x0 = An interrupt has not occurred or is masked. 0x1 = A CIN interrupt has occurred. Advance Encryption Standard Accelerator (AES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 701: Aes_Dmaic Register
Context In DMA Done Raw Interrupt Status. Writing a 1 to this bit clears the CIN bit in the AES_DMARIS and AES_DMAMIS register. SLAU723A – October 2017 – Revised October 2018 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 702 ..................... 10.1 Introduction ....................10.2 Block Diagram ..................10.3 Functional Description ................10.4 Initialization and Configuration ....................10.5 ADC Registers Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 703: Implementation Of Two Adc Blocks
Figure 10-1. Implementation of Two ADC Blocks Figure 10-2 provides details on the internal configuration of the ADC controls and data registers. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 704: Adc Module Block Diagram
FIFO entry is a 32-bit word, with the lower 12 bits containing the conversion result. Table 10-1. Samples and FIFO Depth of Sequencers Sequencer Number of Samples Depth of FIFO Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 705 Digital comparator interrupts are cleared by writing a 1 to the ADC Digital Comparator Interrupt Status and Clear (ADCDCISC) register. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 706: Sample And Hold Width In Adc Clocks
Table 10-2. Sample and Hold Width in ADC Clocks TSHn Encoding Reserved Reserved Reserved Reserved Reserved Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 707: Sample And Hold Width In Adc Clocks
PHASE field in the ADC Sample Phase Control (ADCSPC) register. Figure 10-3 shows an example of various phase relationships. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 708: Adc Sample Phases
Note that it is not required that the TSHn fields be the same in a skewed sample. If an application has varying analog input resistance, then TSHn and PHASE may vary according to operational requirements. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 709: Skewed Sampling
10.5.12). A single averaging circuit has been implemented, thus all input channels receive the same amount of averaging whether they are single-ended or differential. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 710: Sample Averaging Example
Detailed information on the ADC power supplies and analog inputs can be found in the device-specific data sheet. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 711: Adc Voltage Reference
ADC conversion function of the analog inputs. 0xFFF 0xC00 0x800 0x400 - Input Saturation Figure 10-9. ADC Conversion Result SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 712: Differential Sampling Pairs
Thus any difference in common mode between the input voltage and the reference voltage limits the differential dynamic range of the ADC. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 713: Differential Voltage Representation
TSENS © ¹ 1.633 V 0.833 V -40° C 25° C 85° C Temp Figure 10-11. Internal Temperature Sensor Characteristic SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 714 ADC conversions. When the appropriate set of conditions is met, the corresponding digital comparator trigger to the PWM module is asserted. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 715 (Always, Once, Hysteresis Always, and Hysteresis Once) indicates that the interrupt or trigger signal is deasserted and a 1 indicates that the signal is asserted. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 716: Low-Band Operation (Cic = 0X0 Or Ctc = 0X0)
Always ± Once ± Hysteresis Always ± Hysteresis Once ± Figure 10-13. Mid-Band Operation (CIC = 0x1 or CTC = 0x1) Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 717: High-Band Operation (Cic = 0X3 Or Ctc = 0X3)
1. Ensure that the sample sequencer is disabled by clearing the corresponding ASENn bit in the ADCACTSS register. Programming of the sample sequencers is allowed without having them enabled. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 718 6. If interrupts are to be used, set the corresponding MASK bit in the ADCIM register. 7. Enable the sample sequencer logic by setting the corresponding ASENn bit in the ADCACTSS register. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 719: 10.5 Adc Registers
0x090 ADCSSOP2 ADC Sample Sequence 2 Operation Section 10.5.25 0x094 ADCSSDC2 ADC Sample Sequence 2 Digital Comparator Select Section 10.5.26 SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 720: Adc Access Type Codes
Read Type Read Write Type Write 1 to clear Write Reset or Default Value Value after reset or the default value Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 721: Adcactss Register
0x1 = Sample Sequencer 3 is enabled. ASEN2 ADC SS2 Enable. 0x0 = Sample Sequencer 2 is disabled. 0x1 = Sample Sequencer 2 is enabled. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 722 0x1 = Sample Sequencer 1 is enabled. ASEN0 ADC SS0 Enable. 0x0 = Sample Sequencer 0 is disabled. 0x1 = Sample Sequencer 0 is enabled. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 723: Adcris Register
0x0 = The DMA interrupt has not occurred. 0x1 = The sample sequence 0 DMA interrupt is asserted. RESERVED SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 724 0x0 = An interrupt has not occurred. 0x1 = A sample has completed conversion and the respective ADCSSCTL0 IEn bit is set, enabling a raw interrupt. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 725: Adcim Register
0x1 = The raw interrupt signal from the digital comparators (INRDC bit in the ADCRIS register) is sent to the interrupt controller on the SS2 interrupt line. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 726 0x1 = The raw interrupt signal from Sample Sequencer 0 (ADCRIS register INR0 bit) is sent to the interrupt controller. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 727: Adcisc Register
0x1 = Both the INRDC bit in the ADCRIS register and the DCONSS1 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 728 0x1 = Both the INR1 bit in the ADCRIS register and the MASK1 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 729 0x1 = Both the INR0 bit in the ADCRIS register and the MASK0 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 730: Adcostat Register
FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 731: Adcemux Register
0xD = Reserved 0xE = Never Trigger (No triggers are allowed to the ADC digital interface) 0xF = Always (continuously sample) SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 732 0xD = Reserved 0xE = Never Trigger (No triggers are allowed to the ADC digital interface) 0xF = Always (continuously sample) Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 733 0xD = Reserved 0xE = Never Trigger (No triggers are allowed to the ADC digital interface) 0xF = Always (continuously sample) SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 734: Adcustat Register
The valid configurations are the same as those for the UV3 field. This bit is cleared by writing a 1. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 735: Adctssel Register
0x0 = Use Generator 1 (and its trigger) in PWM module 0 0x1 = Reserved 0x2 = Reserved 0x3 = Reserved 11-6 RESERVED SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 736 0x0 = Use Generator 0 (and its trigger) in PWM module 0 0x1 = Reserved 0x2 = Reserved 0x3 = Reserved RESERVED Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 737: Adcsspri Register
The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 738: Adcspc Register
Figure 10-24 and described in Table 10-17. Return to Summary Table. Figure 10-24. ADCSPC Register RESERVED R-0x0 RESERVED PHASE R-0x0 R/W-0x0 Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 739: Adcspc Register Field Descriptions
0xD = The ADC sample lags by 13 clocks 0xE = The ADC sample lags by 14 clocks 0xF = The ADC sample lags by 15 clocks SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 740: Adcpssi Register
0x0 = No effect 0x1 = Begin sampling on Sample Sequencer 2, if the sequencer is enabled in the ADCACTSS register. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 741 0x0 = No effect 0x1 = Begin sampling on Sample Sequencer 0, if the sequencer is enabled in the ADCACTSS register. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 742: Adcsac Register
0x3 = 8x hardware oversampling 0x4 = 16x hardware oversampling 0x5 = 32x hardware oversampling 0x6 = 64x hardware oversampling 0x7 = Reserved Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 743: Adcdcisc Register
This bit is cleared by writing a 1. 0x0 = No interrupt. 0x1 = Digital Comparator 1 has generated an interrupt. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 744 This bit is cleared by writing a 1. 0x0 = No interrupt. 0x1 = Digital Comparator 0 has generated an interrupt. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 745: Adcctl Register
0x0 = VDDA and GNDA are the voltage references for all ADC modules. 0x1 = The external VREFA+ and VREFA- inputs are the voltage references for all ADC modules. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 746: Adcssmux0 Register
The MUX2 field is used during the third sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to- digital conversion. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 747 The MUX0 field is used during the first sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to- digital conversion. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 748: Adcssctl0 Register
0x1 = The temperature sensor is read during the seventh sample of the sample sequence. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 749: Adcssctl0 Register Field Descriptions
If the MASK0 bit in the ADCIM register is set, the interrupt is promoted to the interrupt controller. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 750 0x0 = Another sample in the sequence is the final sample. 0x1 = The third sample is the last sample of the sequence. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 751 0x1 = The analog input is differentially sampled. The corresponding ADCSSMUXn nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 752: Adcssfifon Register
RESERVED DATA R-0x0 Table 10-24. ADCSSFIFOn Register Field Descriptions Field Type Reset Description 31-12 RESERVED 11-0 DATA Conversion Result Data Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 753: Adcssfstatn Register
FIFO, that is, the next entry to be read. Valid values are 0x 0-0x7 for FIFO0 0-0x3 for FIFO1 and FIFO2 and 0x0 for FIFO3. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 754: Adcssop0 Register
Same definition as S7DCOP but used during the second sample. RESERVED S0DCOP Sample 0 Digital Comparator Operation. Same definition as S7DCOP but used during the first sample. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 755: Adcssdc0 Register
Sample 0 Digital Comparator Select. This field has the same encodings as S7DCSEL but is used during the first sample. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 756: Adcssemux0 Register
The EMUX4 field is used during the fifth sample of a sequence executed with the sample sequencer. This bit has the same description as EMUX7. 15-13 RESERVED Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 757: Adcssemux0 Register Field Descriptions
The EMUX0 field is used during the first sample of a sequence executed with the sample sequencer. This bit has the same description as EMUX7. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 758: Adcsstsh0 Register
4th Sample and Hold Period Select. The TSH3 field is used during the fourth sample of a sequence executed with the sample sequencer. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 759 1st Sample and Hold Period Select. The TSH0 field is used during the first sample of a sequence executed with the sample sequencer. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 760: Adcssmuxn Register
4th Sample Input Select 11-8 MUX2 3rd Sample Input Select MUX1 2nd Sample Input Select MUX0 1st Sample Input Select Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 761: Adcssctln Register
0x1 = The analog input is differentially sampled. The corresponding ADCSSMUXn nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 762: Adcssctln Register Field Descriptions
0x1 = The temperature sensor is read during the first sample of the sample sequence. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 763 0x1 = The analog input is differentially sampled. The corresponding ADCSSMUXn nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 764: Adcssop1 Register
Same definition as S3DCOP but used during the second sample. RESERVED S0DCOP Sample 0 Digital Comparator Operation. Same definition as S3DCOP but used during the first sample. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 765: Adcssdcn Register
Sample 0 Digital Comparator Select. This field has the same encodings as S3DCSEL but is used during the first sample. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 766: Adcssemuxn Register
The EMUX1 field is used during the second sample of a sequence executed with the sample sequencer. This bit has the same description as EMUX3. RESERVED Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 767: Adcssemuxn Register Field Descriptions
The EMUX0 field is used during the first sample of a sequence executed with the sample sequencer. This bit has the same description as EMUX3. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 768: Adcsstshn Register
1st Sample and Hold Period Select. The TSH0 field is used during the first sample of a sequence executed with the sample sequencer. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 769: Adcssmux3 Register
MUX0 R-0x0 R/W-0x0 Table 10-38. ADCSSMUX3 Register Field Descriptions Field Type Reset Description 31-4 RESERVED MUX0 1st Sample Input Select. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 770: Adcssctl3 Register
0x1 = The analog input is differentially sampled. The corresponding ADCSSMUXn nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 771: Adcssop3 Register
0x1 = The sample is sent to the digital comparator unit specified by the S0DCSEL bit in the ADCSSDC03 register, and the value is not written to the FIFO. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 772: Adcssdc3 Register
0x5 = Digital Comparator Unit 5 (ADCDCCMP5 and ADCCCTL5) 0x6 = Digital Comparator Unit 6 (ADCDCCMP6 and ADCCCTL6) 0x7 = Digital Comparator Unit 7 (ADCDCCMP7 and ADCCCTL7) Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 773: Adcssemux3 Register
0x1 = The sample input is selected from AIN[23:16] using the ADCSSMUX3 register. For example, if the MUX0 field is 0x0, AIN16 is selected. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 774: Adcsstsh3 Register
1st Sample and Hold Period Select. The TSH0 field is used during the first sample of a sequence executed with the sample sequencer. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 775: Adcdcric Register
0x0 = No effect 0x1 = Resets the Digital Comparator 5 trigger unit to its initial conditions. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 776 0x0 = No effect 0x1 = Resets the Digital Comparator 7 interrupt unit to its initial conditions. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 777 0x0 = No effect 0x1 = Resets the Digital Comparator 1 interrupt unit to its initial conditions. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 778 0x0 = No effect 0x1 = Resets the Digital Comparator 0 interrupt unit to its initial conditions. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 779: Adcdcctln Register
0x1 = Mid BandCOMP0 < ADC Data ≤ COMP1 0x2 = Reserved 0x3 = High BandCOMP0 ≤ COMP1 ≤ ADC Data SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 780 CTC encodings of 0x0 and 0x3. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 781: Adcdccmpn Register
The value in this field is compared against the ADC conversion data. The result of the comparison is used to determine if the data lies within the low-band region. SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 782: Adcpp Register
This field is encoded as a binary value, in the range of 0 to 63. This field provides similar information to the legacy DC3 and DC8 register ADCnAINn bits. Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 783 0x8 = Reserved 0x9 = Reserved 0xA = Reserved 0xC = Reserved 0xD = Reserved 0xE = Reserved 0xF = Reserved SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 784: Adcpc Register
0x8 = Reserved 0x9 = Reserved 0xA = Reserved 0xC = Reserved 0xD = Reserved 0xE = Reserved 0xF = Reserved Analog-to-Digital Converter (ADC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 785: Adccc Register
0x8 = Reserved 0x9 = Reserved 0xA = Reserved 0xC = Reserved 0xD = Reserved 0xE = Reserved 0xF = Reserved SLAU723A – October 2017 – Revised October 2018 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 786 ........................... Topic Page ..................... 11.1 Introduction ....................11.2 Block Diagram ..................11.3 Functional Description ....................11.4 CAN Registers Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 787: Can Controller Block Diagram
CANNWDA2 CANIF2DB1 CANMSG1INT CANIF2DB2 CANMSG2INT CANMSG1VAL CANMSG2VAL Message RAM 32 Message Objects Figure 11-1. CAN Controller Block Diagram SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 788: Can Data Frame Or Remote Frame
In general, one interface is used for transmit data and one for receive data. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 789 (when the number of message objects is not sufficient), the whole message object must be configured before the transmission of this message is requested. SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 790 Note that MSK[12:0] are used for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of the 11-bit message Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 791 CAN IFn Command Request (CANIFnCRQ) register. To begin transmission of the new data as soon as possible, set the TXRQST bit in the CANIFnMSKn register. SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 792: Message Object Configurations
CANIFnMSKn register) for acceptance filtering) not have readily available data. The software must fill the data and answer the frame manually. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 793 The MXTD bit in the CANIFnMSK2 register should be set if only 29-bit extended identifiers are expected by this message object. SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 794 FIFO Buffer can be handled by the CPU. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 795: Message Objects In A Fifo Buffer
(the cause of the interrupt is reset), or until IE is cleared, which disables interrupts from the CAN controller. SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 796 CANnRX signal is disconnected from the CAN Controller and the CANnTX signal is held recessive. This mode is enabled by setting both the LBACK and SILENT bits in the CANTST register. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 797 CAN nodes are able to compensate for the different bit rates by periodically resynchronizing to the bit stream. SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 798: Can Bit Time
SJW bit field. Table 11-3 shows the relationship between the CANBIT register values and the parameters. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 799 The length of the synchronization jump width is set to the least of 4, Phase1, or Phase2. The oscillator tolerance range necessary for the resulting configuration is calculated by the formula given Equation SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 800 1 + tPhase2 = 2 × t (18) tPhase1 = 1 × t (19) tPhase2 = 1 × t (20) \\tPhase2 = tPhase1 Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 801: Canbit Register Values
1 + tPhase2 = 8 × t (38) tPhase1 = 4 × t (39) tPhase2 = 4 × t (40) SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 802: Canbit Register Values For Low Baud Rate Example
= Baud rate prescaler – 1 = 50 – 1 = 49 The final value programmed into the CANBIT register = 0x34F1. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 803: 11.4 Can Registers
Section 11.4.18 0x144 CANMSG2INT CAN Message 2 Interrupt Pending Section 11.4.18 0x160 CANMSG1VAL CAN Message 1 Valid Section 11.4.19 SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 804: Can Access Type Codes
Description Read Type Read Write Type Write Reset or Default Value Value after reset or the default value Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 805: Canctl Register
0x0 = No error status interrupt is generated. 0x1 = A change in the BOFF or EWARN bits in the CANSTS register generates an interrupt. SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 806 0x0 = Interrupts disabled. 0x1 = Interrupts enabled. INIT Initialization. 0x0 = Normal operation. 0x1 = Initialization started. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 807: Cansts Register
0x1 = Since this bit was last cleared, a message has been successfully received, independent of the result of the acceptance filtering. SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 808 0x7 = No EventWhen the LEC bit shows this value, no CAN bus event was detected since this value was written to the LEC field. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 809: Canerr Register
(0 to 127). Transmit Error Counter. This field contains the state of the transmit error counter (0 to 255). SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 810: Canbit Register
2 bit time quanta (1+1). The CANBRPE register can be used to further divide the bit time. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 811: Canint Register
0x0001 to 0x0020 = Number of the message object that caused the interrupt 0x0021 to 0x7FFF = Reserved 0x8000 = Status Interrupt 0x8001 to 0xFFFF = Reserved SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 812: Cantst Register
0x1 = Basic mode is enabled. In basic mode, software should use the CANIF1 registers as the transmit buffer and use the CANIF2 registers as the receive buffer. RESERVED Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 813: Canbrpe Register
1023. The actual interpretation by the hardware is one more than the value programmed by BRPE (MSBs) and BRP (LSBs). SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 814: Canifncrq Register
0x21 to 0x3F = Reserved. Not a valid message number; values are shifted and it is interpreted as 0x01 to 0x1F. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 815: Canifncmsk Register
0x0 = Control bits unchanged. 0x1 = Transfer control bits from the CANIFnMCTL register into the Interface registers. SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 816: Canifncmsk Register Field Descriptions
CANIFnDA2 to the message object.If WRNRD is set, transfer data bytes 4 to 7 in message object to CANIFnDA1 and CANIFnDA2. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 817: Canifnmsk1 Register
0x1 = The corresponding identifier field (ID) is used for acceptance filtering. SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 818: Canifnmsk2 Register
0x1 = The corresponding identifier field (ID) is used for acceptance filtering. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 819: Canifnarb1 Register
[15:0] of the ID, while bits 12:0 of the CANIFnARB2 register are [28:16] of the ID. When using an 11-bit identifier, these bits are not used. SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 820: Canifnarb2 Register
When using an 11-bit identifier, ID[12:2] are used for bits [10:0] of the ID. The ID field in the CANIFnARB1 register is ignored. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 821: Canifnmctl Register
0x1 = The INTPND bit in the CANIFnMCTL register is set after a successful transmission of a frame. SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 822: Canifnmctl Register Field Descriptions
When the message handler stores a data frame, it writes DLC to the value given by the received message. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 823: Canifndnn Register
CANIFnDA2 data bytes 3 and 2; CANIFnDB1 data bytes 5 and 4; and CANIFnDB2 data bytes 7 and 6. SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 824: Cantxrqn Register
0x0 = The corresponding message object is not waiting for transmission. 0x1 = The transmission of the corresponding message object is requested and is not yet done. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 825: Cannwdan Register
0x1 = The message handler or the CPU has written new data into the data portion of the corresponding message object. SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 826: Canmsgnint Register
0x0 = The corresponding message object is not the source of an interrupt. 0x1 = The corresponding message object is the source of an interrupt. Controller Area Network (CAN) Module SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 827: Canmsgnval Register
0x1 = The corresponding message object is configured and should be considered by the message handler. SLAU723A – October 2017 – Revised October 2018 Controller Area Network (CAN) Module Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 828 Page ..................... 12.1 Introduction ....................12.2 Block Diagram ..................12.3 Functional Description ................12.4 Initialization and Configuration ..................12.5 Comparator Registers Analog Comparators SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 829 Compare a test voltage against any one of the following voltages: – An individual external reference voltage – A shared single external reference voltage – A shared internal reference voltage SLAU723A – October 2017 – Revised October 2018 Analog Comparators Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 830: Analog Comparator Module Block Diagram
In addition to an external input, Cn+, input sources for VIN+ can be the C0+ or an internal reference, V IREF Analog Comparators SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 831: Structure Of Comparator Unit
ACCTL ACSTAT Copyright © 2017, Texas Instruments Incorporated Figure 12-2. Structure of Comparator Unit A comparator is configured through two status and control registers, Analog Comparator Control (ACCTL) and Analog Comparator Status (ACSTAT). The internal reference is configured through one control register, Analog Comparator Reference Voltage Control (ACREFCTL).
Page 832: Internal Reference Voltage And Acrefctl Field Values
1.180 1.235 1.290 1.292 1.347 1.402 1.404 1.459 1.514 1.516 1.571 1.627 1.629 1.684 1.739 1.741 1.796 1.851 1.853 1.908 1.963 Analog Comparators SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 833: Analog Comparator Voltage Reference Characteristics
8. Read the comparator output value by reading the OVAL value of the ACSTATn register. 9. Change the level of the comparator negative input signal C- to see the OVAL value change. SLAU723A – October 2017 – Revised October 2018 Analog Comparators Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 834: 12.5 Comparator Registers
Read Type Read Write Type Write 1 to clear Write Reset or Default Value Value after reset or the default value Analog Comparators SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 835: Acmis Register
Comparator 0 Masked Interrupt Status. This bit is cleared by writing a 1. Clearing this bit also clears the IN0 bit in the ACRIS register. SLAU723A – October 2017 – Revised October 2018 Analog Comparators Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 836: Acris Register
This bit is cleared by writing a 1 to the IN1 bit in the ACMIS register. Comparator 0 Interrupt Status. This bit is cleared by writing a 1 to the IN0 bit in the ACMIS register. Analog Comparators SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 837: Acinten Register
Table 12-8. ACINTEN Register Field Descriptions Field Type Reset Description 31:3 RESERVED Comparator 2 Interrupt Enable. Comparator 1 Interrupt Enable. Comparator 0 Interrupt Enable. SLAU723A – October 2017 – Revised October 2018 Analog Comparators Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 838: Acrefctl Register
The voltage corresponding to the tap position is the internal reference voltage available for comparison. See for some output reference voltage examples. Analog Comparators SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 839: Acstatn Register
VIN+ is the voltage on the Cn+ pin, the C0+ pin, or the internal voltage reference (V ) as defined by the ASRCP bit in the ACCTL IREF register. RESERVED SLAU723A – October 2017 – Revised October 2018 Analog Comparators Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 840: Acctln Register
Interrupt Sense. The ISEN field specifies the sense of the comparator output that generates an interrupt. CINV Comparator Output Invert. RESERVED Analog Comparators SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 841: Acmppp Register
Comparator Output 1 Present. Comparator Output 0 Present. 15:3 RESERVED CMP2 Comparator 2 Present. CMP1 Comparator 1 Present. CMP0 Comparator 0 Present. SLAU723A – October 2017 – Revised October 2018 Analog Comparators Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 842 ........................... Topic Page ..................... 13.1 Introduction ..................13.2 Functional Description ................13.3 Initialization and Configuration ....................13.4 CRC Registers Cyclical Redundancy Check (CRC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 843 The data size is configured by programming the SIZE bit in the CRCCTRL register, offset 0x400. SLAU723A – October 2017 – Revised October 2018 Cyclical Redundancy Check (CRC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 844: Endian Configuration
CRCCTRL register is set to select byte, the CRC engine operates in byte mode and only the least significant byte is used for CRC calculation. Cyclical Redundancy Check (CRC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 845 – {D3, D2, D1, D0} – {D7, D6, D5, D4} – {D11, D10, D9, D8} – ..– ..SLAU723A – October 2017 – Revised October 2018 Cyclical Redundancy Check (CRC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 846: 13.4 Crc Registers
Code Description Read Type Read Write Type Write Reset or Default Value Value after reset or the default value Cyclical Redundancy Check (CRC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 847: Crcctrl Register
0h = No change to result. 1h = Bit reverse the input byte for all bytes in a word. RESERVED SLAU723A – October 2017 – Revised October 2018 Cyclical Redundancy Check (CRC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 848 0h = Polynomial 0x8005 1h = Polynomial 0x1021 2h = Polynomial 0x4C11DB7 3h = Polynomial 0x1EDC6F41 8h = TCP checksum Cyclical Redundancy Check (CRC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 849: Crcseed Register
This register contains the starting seed of the CRC and checksum operation. This register also holds the latest result of CRC or checksum operation. SLAU723A – October 2017 – Revised October 2018 Cyclical Redundancy Check (CRC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 850: Crcdin Register
Reset Description 31-0 DATAIN Data Input. This register contains the input data value for the CRC or checksum operation. Cyclical Redundancy Check (CRC) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 851: Crcrsltpp Register
Table 13-8. CRCRSLTPP Register Field Descriptions Field Type Reset Description 31-0 RSLTPP Post Processing Result. This register contains the post-processed CRC result. SLAU723A – October 2017 – Revised October 2018 Cyclical Redundancy Check (CRC) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 852 DES Module Programming Guide – Low Level Programming Models ....................14.7 DES Registers ..................14.8 DES µDMA Registers Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 853: Key Repartition
✓ ✓ ✓ ✓ ✓ ECB, CBC, and CFB modes can be used with DES and 3DES modes. SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 854: Des Block Diagram
Interrupt Enable (DES_IRQENABLE) register. The following events can generate an interrupt bit to be set in the DES_IRQSTATUS register: • New context input required • Data input required • Data output ready Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 855 The DES Cipher Core has a standard lookup table S-Box that allows room for the synthesizer to optimize on timing or gate count. SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 856: Des - Ecb Feedback Mode
Output Buffer Output Buffer (plain text) (plain text) Encryption Decryption Figure 14-2. DES – ECB Feedback Mode Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 857: Des3Des - Cbc Feedback Mode
Register Output Buffer Output Buffer (plain text) (plain text) Decryption Encryption Figure 14-4. DES3DES – CFB Feedback Mode SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 858: Des Global Initialization
Table 14-4. DES Algorithm Type Configuration Step Register/Bit Field / Programming Model Value DES_KEY1_L[31:0] KEY1_L DES_KEY1_H[31:0] KEY1_H DES_CTRL[3] TDES Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 859: 3Des Algorithm Type Configuration
Figure 14-5 shows DES polling mode. The registers used in DES polling mode are: DES_DATA_L, DES_DATA_H, and DES_CTRL. SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 860: Des Polling Mode
Table 14-6. DES Interrupt Mode Step Register / Bit Field / Programming Model Value DES_IRQENABLE[2:0] DES_DATA_L[31:0] DATA_L DES_DATA_H[31:0] DATA_H Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 861: Des Interrupt Service
Encrypt/Decrypted data DES_S_DATA_L[31:0] DATA_L DES_S_DATA_H[31:0] DATA_H Clear interrupt status DES_S_IRQSTATUS[2:0] = 0x0 Figure 14-6. DES Interrupt Service SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 862: Des Context Input Event Service
DES_S_IV_L[31:0]IV_L=0x- DES_S_IV_H[31:0] IV_H=0x- Load crypto data length DES_S_LENGTH[31:0] LENGTH = 0x- Figure 14-7. DES Context Input Event Service Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 863: 14.7 Des Registers
Write Type Write 1 to clear Write Reset or Default Value Value after reset or the default value SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 864: Des_Keyn_N Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R/W-0x0 Table 14-10. DES_KEYn_n Register Field Descriptions Field Type Reset Description 31-0 Key data Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 865: Des_Iv_L Register
Table 14-11. DES_IV_L Register Field Descriptions Field Type Reset Description 31-0 IV_L Initialization vector for CBC, CFB modes (LSW) SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 866: Des_Iv_H Register
Table 14-12. DES_IV_H Register Field Descriptions Field Type Reset Description 31-0 IV_H Initialization vector for CBC, CFB modes (MSW) Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 867: Des_Ctrl Register
0x1 = Encryption is selected INPUT_READY When 1, ready to encrypt or decrypt data OUTPUT_READY When 1, Data decrypted/encrypted ready SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 868: Des_Length Register
Table 14-14. DES_LENGTH Register Field Descriptions Field Type Reset Description 31-0 LENGTH Cryptographic data length in bytes for all modes Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 869: Des_Data_L Register
DATA_L R/W-0x0 Table 14-15. DES_DATA_L Register Field Descriptions Field Type Reset Description 31-0 DATA_L Data for encryption/decryption, LSW SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 870: Des_Data_H Register
DATA_H R/W-0x0 Table 14-16. DES_DATA_H Register Field Descriptions Field Type Reset Description 31-0 DATA_H Data for encryption/decryption, MSW Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 871: Des_Revision Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 REVISION R-0x21 Table 14-17. DES_REVISION Register Field Descriptions Field Type Reset Description 31-0 REVISION 0x21 Revision number SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 872: Des_Sysconfig Register
Sidle mode 0x0 = reserved SOFTRESET Soft reset 0x0 = No operation 0x1 = Start soft reset sequence RESERVED Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 873: Des_Sysstatus Register
Type Reset Description 31-1 RESERVED RESETDONE Reset Done 0x0 = Reset is not complete 0x1 = Reset done SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 874: Des_Irqstatus Register
This bit indicates data input interrupt is active and triggers the interrupt output. CONTEX_IN This bit indicates context interrupt is active and triggers the interrupt output. Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 875: Des_Irqenable Register
If this bit is set to 1 the data input interrupt is enabled. M_CONTEX_IN If this bit is set to 1 the context interrupt is enabled. SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 876: Des_Dirtybits Register
This bit is set to 1 by the module if any of the DES_* registers is read. Except DES_DIRTYBITS and DES_LOCKDOWN. Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 877: Des Μdma Access Type Codes
Write Type Write 1 to clear Write Reset or Default Value Value after reset or the default value SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 878: Des_Dmaim Register
0x0 = The CIN interrupt is suppressed and not sent to the interrupt controller. 0x1 = The CIN interrupt is sent to the interrupt controller. Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 879: Des_Dmaris Register
0x1 = The µDMA has completed a context write to the internal register and an interrupt has been triggered and is pending. SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 880: Des_Dmamis Register
Context In DMA Done Raw Interrupt Status 0x0 = An interrupt has not occurred or is masked. 0x1 = A CIN interrupt has occurred. Data Encryption Standard Accelerator (DES) SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 881: Des_Dmaic Register
Context In DMA Done Raw Interrupt Status Writing a 1 to this bit clears the CIN bit in the DES_DMARIS and DES_DMAMIS register. SLAU723A – October 2017 – Revised October 2018 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 882 Functional Description ....................15.4 Ethernet PHY ................15.5 Initialization and Configuration ....................15.6 EMAC Registers ..............15.7 MII Management (EPHY) Registers 1045 Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 883 – MDI/MDI-X cross-over support – Register-programmable transmit amplitude – Automatic polarity correction and 10BASE-T signal reception • MII and RMII interface support SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 884: Ethernet Mac With Integrated Phy Interface
The MOSC source can be a single-ended source or a crystal. Figure 15-2 shows the clock inputs to the Ethernet Controller module. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 885: Ethernet Mac And Phy Clock Structure
10 Mbps or 100 Mbps. Figure 15-3 shows the clock inputs for an MII. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 886: Mii Clock Structure
Mbps, or 2 for 100 Mbps operation, and used as the clock for receive and transmit data. Figure 15-4 shows the clock inputs to the RMII clock. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 887: Rmii Clock Structure
EN0RXD0 RXD0: Receive Data 0 EN0RXDV EN0RXDV CRS_DV: Carrier Sense/Receive Data Valid EN0RXER Not used RX_ER: Receive Error EN0COL Not used SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 888 This enables two buffers to be used at different physical addresses rather than contiguous buffers in memory. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 889 Receive buffer of the frame. The DMA ignores the offset address and performs full word writes for the middle and the last Receive buffer of the frame. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 890 Alternate Descriptor Size (ATDS) bit in the Ethernet MAC DMA Bus Mode (EMACDMABUSMOD) register. Section 15.3.3.5.1 Section 15.3.3.5.2 for more details on the descriptor structure. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 891: Enhanced Transmit Descriptor Structure
TDES2 contains the address pointer to the first buffer of the descriptor (see Table 15-4). • TDES3 contains the address pointer either to the second buffer of the descriptor or the next descriptor SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 892: Enhanced Transmit Descriptor 0 (Tdes0)
When set, this bit indicates that the second address in the descriptor is the Next Descriptor address rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a "don't care" value. TDES0[21] takes precedence over TDES0[20]. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 893 This 4-bit counter value indicates the number of collisions occurring before the frame was transmitted. The count is not valid when the Excessive Collision bit (TDES0[8]) is set. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 894: Enhanced Transmit Descriptor 1 (Tdes1)
The buffer address pointer must be aligned to the bus width only when TDES0[20] is set. Note that the buffers are stored in SRAM. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 895: Enhanced Transmit Descriptor 6 (Tdes6)
(0), the TDES4-TDES7 descriptor space is not valid and only Alternate Descriptors are available, with a default size of 16 bytes (4 words). SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 896: Enhanced Receive Descriptor Structure
The inclusion of CRC length in the frame length depends on the settings of CRC configuration bits, ACS and CST in the EMACCFG register. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 897 When set, this bit indicates that the Receive Watchdog Timer has expired while receiving the current frame and the current frame is truncated after the Watchdog Timeout. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 898: Rdes0 Checksum Offload Bits
When this bit is set, RBS2 (RDES1[28:16]) is a "don't care" value. RDES1[15] takes precedence over RDES1[14]. Reserved Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 899: Enhanced Receive Descriptor 2 (Rdes2)
PTP message is sent over UDP-IPv4 or UDP-IPv6. The information about IPv4 or IPv6 can be obtained from Bits 6 and 7. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 900: Enhanced Receive Descriptor 6 (Rdes6)
This field is updated by the DMA only for the last descriptor of the receive frame which is indicated by Last Descriptor status bit (RDES0[8]). Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 901: Enhanced Receive Descriptor 7 (Rdes7)
CPU stopped the DMA by clearing the ST bit of the EMACDMAOPMODE register, the DMA enters the STOP state. Figure 15-7 shows the flow for the TX DMA default operation. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 902: Tx Dma Default Operation Using Descriptors
If the second frame is valid, the transmit process transfers this frame before writing the first frame's status information. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 903 Therefore, the descriptor chain should have more than two different descriptors for correct and proper operation. Figure 15-8 shows the flow for the TX DMA Operate-On-Second-Frame (OSF) operation. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 904: Tx Dma Osf Mode Operation Using Descriptors
First Segment Descriptor and the Last Segment Descriptor, respectively. The First Descriptor bit is located at TDES0[28] and the Last Descriptor is located at TDES0[29]. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 905 EMACDMAOPMODE register). The DMA closes the current descriptor (clears the OWN bit) and marks it as intermediate by clearing the Last Segment (LS) bit in the RDES0 value. If flushing is not disabled, SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 906 RDES7. Otherwise if timestamping is not enabled, RDES6 and RDES7 remain unchanged. Figure 15-9 shows the flow of a RX DMA Operation. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 907: Rx Dma Operation Flow
RSED6 and RDES7 present? intermediate descriptor Close RDES0 as Error last descriptor condition? Start=0 Error condition? Figure 15-9. RX DMA Operation Flow SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 908 – Transmit Buffer Unavailable (TU, bit 2): Indicates the CPU owns the next descriptor in the transmit list and the DMA cannot acquire it. – Receive Interrupt (RI, bit 6): Indicates the frame reception is complete. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 909 At reset, the TX/RX Controller is configured and ready to manage data flow to and from the DMA to the MAC. Note that the DMA and MAC must be initialized by the application out of reset. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 910 EOF is transferred to the TX/RX Controller from the DMA. This enables the TX/RX Controller to retry transmission of the frame data from the FIFO. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 911 NOTE: The timestamp transfer takes two clock cycles and the lower 32-bits of the timestamp are sent first when timestamping is enabled. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 912: Tx Mac Flow Control
Table 15-17. RX MAC Flow Control TFE Bit in DUPM Bit in Description EMACFLOWCTL EMACCFG The MAC receiver does not detect the received Pause frames. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 913 TX FIFO. The preamble is defined as 7 bytes of 0xAA and the SFD is defined as 1 byte of 0xAB pattern. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 914 The receive CRC Generator is used to generate the 32-bit CRC for the FCS field of the Ethernet frame. The encoding is defined by the following generating polynomial: Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 915 Figure 15-10 shows the process that PTP uses for synchronizing a slave node to a master node by exchanging PTP messages. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 916: Networked Time Synchronization
PTP packets enter or leave the Ethernet MAC. This timing information is captured and returned to the software for the proper implementation of PTP with high accuracy. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 917: System Time Update Using Fine Correction Method
Timestamp Addend Register (TSAR) field in the EMACTIMADD register. This value is calculated as: FreqCompensationValue = TSAR = 2 / FreqDivisionRatio (50) SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 918 RDES7), indicating that the timestamp is not correct. If timestamping is disabled, the DMA does not alter RDES6 or RDES7. RDES0[7] indicates whether the timestamp is updated in RDES6 and RDES7. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 919 Request, Follow-up, and Delay Response messages. Figure 15-12 shows the method to calculate the propagation delay in clocks supporting peer-to-peer path correction. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 920: Propagation Delay Calculation In Clocks Supporting Peer-To-Peer Path Correction
For an ordinary clock, snapshots can be taken of either version 1 or version 2 PTP types but not both. Selecting between the two is controlled by the PTPVER2 bit of the EMACTIMSTCTRL register. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 921 (EMACPPS0INTVL) register, offset 0x760. You can program the interval between pulses from 1 to 2 1 units of subsecond increment value. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 922 The frame filtering supports a sequence where the packet is not forwarded to VLAN filtering if it does not pass the SA or DA filtering first. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 923: Vlan Match Status
Fail Fail Fail Fail Fail Pass Pass VL ! = 0 Fail Pass Pass Fail Fail Pass Fail Fail Fail Pass SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 924 VLAN insertion control is enabled, the MAC appends or replaces the FCS field with the computed CRC when Disable CRC Control is enabled or disabled, respectively. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 925: Crc Replacement Based On Bit 27 And Bit 24 Of Tdes0
If the checksum offload engine detects an IP header error, it still inserts an IPv4 header checksum if the Ethernet Type field indicates an IPv4 payload. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 926 The current pointer value of the bank is updated in the Remote Wake-Up FIFO Pointer (RWKPTR) field of the Ethernet MAC PMT Control and Status (EMACPMTCTLSTAT) register. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 927: Wake-Up Frame Filter Register Bank
Ethernet MAC Remote Wake-Up Frame Filter (EMACRWUFF) register. The Power Management (PMT) block supports four programmable filters that allow support of SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 928 1. Disable the Transmit DMA (if applicable) and wait for any previous frame transmissions to complete. These transmissions can be detected when TI is set in the Ethernet MAC DMA Interrupt Status (EMACDMARIS) register. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 929 IEEE 802.3, but maintains high margins in terms of alien cross-talk. The following highlights the features of the PHY module: • Cable Diagnostics SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 930: Integrated Phy Diagram
The PHY supports four different Ethernet protocols (10Mbs Half- Duplex, 10Mbs Full-Duplex, 100Mbs Half-Duplex, and 100Mbs Full-Duplex). Auto-Negotiation selects the Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 931: Forced Mode Configurations
Link OK (0x0) • RX/TX Activity (0x1) • TX Activity (0x2) • RX Activity (0x3) • Collision (0x4) • 100-BASE TX speed (0x5) SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 932 The following sections describe how to perform operations on the extended register set using the EPHYREGCTL and EPHYADDAR registers. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 933 The DEVAD field of the EPHYREGCTL register identifies the device address, which is 0x1F, for the integrated PHY. The FUNC field of the EPHYREGCTL register should be set to 0x1 to indicate SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 934 0x1F are available for external PHYs. • MII: Register address of PHY register to be written. • CR: Clock Reference for the MDIO interface. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 935: Interface To Ethernet Jack
1. Enable the external clock source input to the RMII interface signal EN0RREF_CLK by setting both the ECEXT and CLKEN bit in the in the Ethernet Clock Configuration (EMACCC) register at offset 0xFC8. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 936: Emacpc To Phy Register Mapping
The mappings of the EMACPC register bits to the PHY register and bits are as follows: Table 15-22. EMACPC to PHY Register Mapping Corresponding PHY Bit (Bit EMACPC Register Bit Corresponding PHY Register No.) PHYEXT DIGRESTART Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 937 0x930. When the R0 bit reads as 1 in the PREPHY register at System Control offset 0xA30, the PHY registers are ready for programming. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 938 NOTE: If a software reset is asserted to the PHY afterwards through the SREPHY register, the custom configuration is lost and the steps described above must be repeated. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 939: 15.6 Emac Registers
Ethernet MAC Receive Frame Count for Good and Bad Section 15.6.34 Frames 0x194 EMACRXCNTCRCERR Ethernet MAC Receive Frame Count for CRC Error Section 15.6.35 Frames SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 940 Complex bit access types are encoded to fit into small table cells. Table 15-24 shows the codes that are used for access types in this section. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 941: Emac Access Type Codes
Read Type Read Write Type Write 1 to clear Write Reset or Default Value Value after reset or the default value SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 942: Emaccfg Register
0x7 = The MAC replaces the content of the Ethernet MAC Address 1(EMACADDR1x) registers in the source address (SA) field for all transmitted frames. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 943 0x0 = Generate errors for carrier sense errors. 0x1 = Ignore carrier sense errors. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 944 0x0 = All frames are passed to host unmodified. 0x1 = MAC strips FCS field if value of length field is less than 1,536 bytes. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 945 0x0 = 7 bytes of preamble 0x1 = 5 bytes of preamble 0x2 = 3 bytes of preamble 0x3 = Reserved SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 946: Emacframefltr Register
0x0 = Address filter passes a frame if it matches perfect filtering or hash filtering. 0x1 = Address filter passes a frame only if it matches in the hash filter. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 947: Emacframefltr Register Field Descriptions
0x0 = Normal filtering of frames is performed. 0x1 = Inverse filtering mode is enabled for DA. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 948 Word are always cleared when PR is set. 0x0 = Incoming frames are filtered. 0x1 = All incoming frames are passed. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 949: Emachashtblh Register
Table 15-27. EMACHASHTBLH Register Field Descriptions Field Type Reset Description 31-0 Hash Table High. This field contains the upper 32 bits of the hash table. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 950: Emachashtbll Register
Table 15-28. EMACHASHTBLL Register Field Descriptions Field Type Reset Description 31-0 Hash Table Low. This field contains the lower 32 bits of the hash table. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 951: Emacmiiaddr Register
0x0 = Read operation is active and read data is placed in the MII Data register (EMACMIIDATA). 0x1 = PHY is notified that this is a write operation using the MII Data Register (EMACMIIDATA). SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 952 0x0 = EMACMIIADDR and EMACMIIDATA are available for reads and writes. 0x1 = Read or write access is in progress. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 953: Emacmiidata Register
16-bit data value to be written to the PHY before a management write operation. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 954: Emacflowctl Register
0x0 = The decode function of the pause frame is disabled. 0x1 = The MAC decodes the received pause frame and disables its transmitter for a specified (pause) time. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 955: Emacflowctl Register Field Descriptions
0x1 = In the full-duplex mode, a pause control frame is enabled. In half-duplex mode, a back-pressure function is enabled if the TFE bit is set. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 956: Emacvlantg Register
Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 957: Emacvlantg Register Field Descriptions
16th bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 or 0x88A8 as VLAN frames. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 958: Emacstatus Register
0x1 = Indicates that the MAC transmitter is in the PAUSE condition (in the full-duplex only mode) and hence does not schedule any frame for transmission. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 959: Emacstatus Register Field Descriptions
0x0 = MAC MII receive protocol engine is not actively receiving data. 0x1 = Indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 960: Emacrwuff Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 WAKEUPFIL R/W-0x0 Table 15-34. EMACRWUFF Register Field Descriptions Field Type Reset Description 31-0 WAKEUPFIL Remote Wake-Up Frame Filter. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 961: Emacpmtctlstat Register
0x1 = The power management event is generated because of the reception of a magic packet.This bit is cleared whenever the register is read. RESERVED SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 962: Emacpmtctlstat Register Field Descriptions
0x0 = Frames are forwarded to application. 0x1 = MAC receiver drops all received frames until it receives the expected magic packet or wake-up frame. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 963: Emaclpictlstat Register
This bit is reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. 0x0 = MAC ignores link status bits 0x1 = MAC uses link status bits SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 964: Emaclpictlstat Register Field Descriptions
0x0 = MAC transmitter not in LPI mode 0x1 = MAC transmitter entered the LPI mode because of the setting of the LPIEN bit Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 965: Emaclpitimerctrl Register
LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after this timer expires. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 966: Emacris Register
0x0 = No interrupts exist in the MAC MMC Transmit Interrupt (EMACMMCTXRIS) register. 0x1 = Indicates an interrupt has been generated in the MAC MMC Transmit Interrupt (EMACMMCTXRIS) register. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 967 0x1 = Indicates a Magic packet or Wake-on-LAN frame is received in the power-down mode (see Bits 5 and 6 in the MACPMTCTRLSTAT register). RESERVED SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 968: Emacim Register
0x1 = The assertion of the PMT interrupt status bit in the MAC Raw Interrupt Status (EMACRIS) register is masked and does not cause an interrupt. RESERVED Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 969: Emacaddr0H Register
6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (PAUSE) Frames. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 970: Emacaddr0L Register
6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (PAUSE) Frames. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 971: Emacaddr1H Register
RESERVED 15-0 ADDRHI 0xFFFF MAC Address1 [47:32]. This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 972: Emacaddr1L Register
MAC Address1 [31:0]. This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 973: Emacaddr2H Register
RESERVED 15-0 ADDRHI 0xFFFF MAC Address2 [47:32]. This field contains the upper 16 bits [47:32] of the third 6-byte MAC address. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 974: Emacaddr2L Register
MAC Address2 [31:0]. This field contains the lower 32 bits of the third 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 975: Emacaddr3H Register
RESERVED 15-0 ADDRHI 0xFFFF MAC Address3 [47:32]. This field contains the upper 16 bits [47:32] of the fourth 6-byte MAC address. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 976: Emacaddr3L Register
MAC Address3 [31:0]. This field contains the lower 32 bits of the fourth 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 977: Emacwdogto Register
1522 (0x05F2). Otherwise, valid tagged IEEE 802.3 frames are declared as error frames and are dropped. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 978: Emacmmcctrl Register
0x1 = All counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit. The CNTPRST bit is cleared automatically after 1 clock cycle. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 979: Emacmmcctrl Register Field Descriptions
Counters Reset. 0x0 = No effect 0x1 = All MMC counters are reset. This bit is cleared automatically after one clock cycle. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 980: Emacmmcrxris Register
0x1 = The Ethernet MAC Receive Frame Count for Alignment Error Frames (EMACRXCNTALGNERR) register has reached half of the maximum value or the maximum value. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 981: Emacmmcrxris Register Field Descriptions
0x1 = The Ethernet MAC Receive Frame Count for Good and Bad Frames (EMACRXCNTGB) register has reached half of the maximum value or the maximum value. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 982: Emacmmctxris Register
0x1 = The Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision (EMACTXCNTSCOL) register has reached half of the maximum value or the maximum value. 13-2 RESERVED Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 983: Emacmmctxris Register Field Descriptions
0x1 = The Ethernet MAC Transmit Frame Count for Good and Bad Frames (EMACTXCNTGB) register has reached half of the maximum value or the maximum value. RESERVED SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 984: Emacmmcrxim Register
0x0 = An interrupt is sent to the interrupt controller when the GBF bit in the EMACMMCRXRIS register is set. 0x1 = The GBF interrupt is suppressed and not sent to the interrupt controller. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 985: Emacmmctxim Register
EMACMMCTXRIS register is set. 0x1 = The GBF interrupt is suppressed and not sent to the interrupt controller. RESERVED SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 986: Emactxcntgb Register
Field Type Reset Description 31-0 TXFRMGB This field indicates the number of good and bad frames transmitted, exclusive of retried frames. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 987: Emactxcntscol Register
Reset Description 31-0 TXSNGLCOLG This field indicates the number of successfully transmitted frames after a single collision in the half-duplex mode. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 988: Emactxcntmcol Register
Type Reset Description 31-0 TXMULTCOLG This field indicates the number of successfully transmitted frames after multiple collisions in the half-duplex mode. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 989: Emactxoctcntg Register
Table 15-57. EMACTXOCTCNTG Register Field Descriptions Field Type Reset Description 31-0 TXOCTG This field indicates the number of bytes transmitted, exclusive of preamble, in good frames. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 990: Emacrxcntgb Register
Table 15-58. EMACRXCNTGB Register Field Descriptions Field Type Reset Description 31-0 RXFRMGB This field indicates the number of received good and bad frames. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 991: Emacrxcntcrcerr Register
Table 15-59. EMACRXCNTCRCERR Register Field Descriptions Field Type Reset Description 31-0 RXCRCERR This field indicates the number of frames received with CRC error. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 992: Emacrxcntalgnerr Register
Table 15-60. EMACRXCNTALGNERR Register Field Descriptions Field Type Reset Description 31-0 RXALGNERR This field indicates the number of frames received with alignment (dribble) error. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 993: Emacrxcntguni Register
Table 15-61. EMACRXCNTGUNI Register Field Descriptions Field Type Reset Description 31-0 RXUCASTG This field indicates the number of received good unicast frames. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 994: Emacvlnincrep Register
Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag's VID field. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 995: Emacvlanhash Register
Table 15-63. EMACVLANHASH Register Field Descriptions Field Type Reset Description 31-16 RESERVED 15-0 VLHT VLAN Hash Table. This field contains the 16-bit VLAN Hash Table. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 996: Emactimstctrl Register
0x0 = The MAC ignores PTP transported over UDP-IPv6 packets. 0x1 = The MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 997: Emactimstctrl Register Field Descriptions
0x0 = Indicates the system timestamp update should be done using the coarse method. 0x1 = Indicates that the system times update should be done using the fine update method. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 998 0x1 = The timestamp is added for the transmit and receive frames Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 999: Emacsubsecinc Register
EMACTIMNANO register has a resolution of ~0.465ns. In this case, a value of 86 (0x56), that is derived by 40ns/0.465, should be programmed in the SSINC field. SLAU723A – October 2017 – Revised October 2018 Ethernet Controller Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...
Page 1000: Emactimsec Register
Timestamp Second. The value in this field indicates the current value in seconds of the system time maintained by the MAC. 1000 Ethernet Controller SLAU723A – October 2017 – Revised October 2018 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated...

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