Texas Instruments TMS570LC4357 Manuals

Manuals and User Guides for Texas Instruments TMS570LC4357. We have 1 Texas Instruments TMS570LC4357 manual available for free PDF download: Technical Reference Manual

Texas Instruments TMS570LC4357 Technical Reference Manual (2208 pages)

TMS570LC43 Series 16/32-Bit RISC Flash Microcontrollers

Brand: Texas Instruments | Category: Microcontrollers | Size: 14 MB

Table of Contents
2
Preface

104
1 Introduction

106
- Designed for Safety Applications
  107
- Family Description
  108
- Endianism Considerations
  111
  - TMS570: Big Endian (BE32)
    111
2 Architecture

112
- Introduction
  113
  - Architecture Block Diagram
    113
  - Definitions of Terms
    115
  - Bus Master / Slave Access Privileges
    118
  - CPU Interconnect Subsystem SDC MMR Port
    118
  - Interconnect Subsystem Runtime Status
    119
  - Master ID to Pcrx
    119
- Memory Organization
  120
  - Memory-Map Overview
    120
  - Memory-Map Table
    122
  - Flash on Microcontrollers
    129
  - On-Chip SRAM
    134
- Exceptions
  139
  - Resets
    139
  - Aborts
    139
  - System Software Interrupts
    141
- Clocks
  142
  - Clock Sources
    142
  - Clock Domains
    143
  - Low Power Modes
    145
  - Clock Test Mode
    146
  - Embedded Trace Macrocell (ETM-R5)
    148
  - Safety Considerations for Clocks
    148
- System and Peripheral Control Registers
  151
3 SCR Control Module (SCM)

252
- Overview
  253
  - Features
    253
  - System Block Diagram
    254
- Module Operation
  255
  - Block Diagram
    255
  - Timeout Threshold Compare Block
    255
  - SCM Control Block
    256
- How to Use SCM
  257
- SCM Registers
  260
4 Interconnect

265
5 Power Management Module (PMM)

279
6 I/O Multiplexing and Control Module (IOMM)

301
7 F021 Level 2 Flash Module Controller (L2FMC)

338
8 Level 2 RAM (L2RAMW) Module

387
9 Programmable Built-In Self-Test (PBIST) Module

405
- Overview
  406
  - Features of PBIST
    406
  - PBIST Vs. Application Software-Based Testing
    406
  - PBIST Block Diagram
    406
- RAM Grouping and Algorithm
  407
- PBIST Flow
  408
  - PBIST Sequence
    409
- Memory Test Algorithms on the On-Chip ROM
  411
- PBIST Control Registers
  412
- PBIST Configuration Example
  426
  - Example 1 : Configuration of PBIST Controller to Run Self-Test on DCAN1 RAM
    426
  - Example 2 : Configuration of PBIST Controller to Run Self-Test on ALL RAM Groups
    427
10 Self-Test Controller (STC) Module

428
11 System Memory Protection Unit (NMPU)

460
- Overview
  461
  - Features
    461
  - Safety Diagnostic
    461
  - Block Diagram
    462
- Module Operation
  463
  - Functional Mode
    463
  - Diagnostic Mode
    465
  - Functional Fail Safe
    465
- How to Use NMPU
  466
  - How to Use NMPU in Functional Mode
    466
  - How to Use Diagnostics
    468
- NMPU Registers
  471
- MPU Revision ID Register (MPUREV)
  472
12 Error Profiling Controller (EPC)

483
- Overview
  484
- Module Operation
  484
  - Uncorrectable Fault Operation
    485
  - Correctable Fault Operation
    485
- How to Use EPC
  487
  - Functional Mode
    487
  - CAM Diagnostic Mode
    488
- EPC Control Registers
  488
13 CPU Compare Module for Cortex-R5F (CCM-R5F)

497
- Overview
  498
  - Main Features
    498
  - Block Diagram
    498
- Module Operation
  499
  - CPU/VIM Output Compare Diagnostic
    500
  - CPU Input Inversion Diagnostic
    504
  - Checker CPU Inactivity Monitor
    505
  - Power Domain Inactivity Monitor
    507
  - Operation During CPU Debug Mode
    507
- Control Registers
  507
14 Oscillator and PLL

517
- Introduction
  518
  - Features
    518
- Quick Start
  519
- Oscillator
  520
  - Oscillator Implementation
    521
  - Oscillator Enable
    521
  - Oscillator Disable
    521
- Low Power Oscillator and Clock Detect (LPOCLKDET)
  522
  - Clock Detect
    522
  - Behavior on Oscillator Failure
    522
  - Recovery from Oscillator Failure
    523
  - LPOCLKDET Enable
    523
  - LPOCLKDET Disable
    524
  - Trimming the HF LPO Oscillator
    524
- Pll
  525
  - Modulation
    527
  - PLL Output Control
    528
  - Behavior on PLL Fail
    531
  - Recovery from a PLL Failure
    532
  - PLL Modulation Depth Measurement
    533
  - PLL Frequency Measurement Circuit
    533
  - Pll2
    533
- PLL Control Registers
  534
- Phase-Locked Loop Theory of Operation
  538
  - Phase-Frequency Detector
    538
  - Charge Pump and Loop Filter
    539
  - Voltage-Controlled Oscillator
    539
  - Frequency Modulation
    540
- Programming Example
  540
15 Dual-Clock Comparator (DCC) Module

542
- Introduction
  543
  - Main Features
    543
  - Block Diagram
    543
- Module Operation
  544
  - Continuous Monitoring Mode
    544
  - Single-Shot Measurement Mode
    547
- Clock Source Selection for Counter0 and Counter1
  548
- DCC Control Registers
  549
17 Real-Time Interrupt (RTI) Module

583
21 External Memory Interface (EMIF)

794
- Introduction
  794
- Purpose of the Peripheral
  794
- Features
  794
- Functional Block Diagram
  795
- EMIF Module Architecture
  796
- EMIF Clock Control
  796
- EMIF Requests
  796
- EMIF Signal Descriptions
  796
- EMIF Signal Multiplexing Control
  797
- SDRAM Controller and Interface
  798
- Asynchronous Controller and Interface
  810
- Data Bus Parking
  822
- Reset and Initialization Considerations
  823
- Interrupt Support
  823
- DMA Event Support
  824
- EMIF Signal Multiplexing
  824
- Memory Map
  824
- Priority and Arbitration
  825
- System Considerations
  826
- Power Management
  827
- Emulation Considerations
  827
- EMIF Registers
  828
- Module ID Register (MIDR)
  828
- Asynchronous Wait Cycle Configuration Register (AWCC)
  829
- SDRAM Configuration Register (SDCR)
  830
- SDRAM Refresh Control Register (SDRCR)
  831
- Asynchronous N Configuration Registers (CE2CFG-CE5CFG)
  832
- SDRAM Timing Register (SDTIMR)
  833
- SDRAM Self Refresh Exit Timing Register (SDSRETR)
  834
- EMIF Interrupt Raw Register (INTRAW)
  835
- EMIF Interrupt Masked Register (INTMSK)
  836
- EMIF Interrupt Mask Set Register (INTMSKSET)
  837
- EMIF Interrupt Mask Clear Register (INTMSKCLR)
  838
- Page Mode Control Register (PMCR)
  839
- Example Configuration
  840
- Hardware Interface
  840
- Software Configuration
  840
- Analog to Digital Converter (ADC) Module
  848
22 Analog to Digital Converter (ADC) Module

849
23 High-End Timer (N2HET) Module

954
- Overview
  954
- Features
  954
- Major Advantages
  954
- Block Diagram
  955
- Timer Module Structure and Execution
  956
- Performance
  957
- N2HET Compared to NHET
  957
- NHET and N2HET Compared to HET
  957
- Instructions Features
  958
- Program Usage
  958
- N2HET Functional Description
  958
- Specialized Timer Micromachine
  958
- N2HET RAM Organization
  963
- Time Base
  966
- Host Interface
  969
- I/O Control
  970
- Suppression Filters
  986
- Interrupts and Exceptions
  987
- Hardware Priority Scheme
  988
- N2HET Requests to DMA and HTU
  990
- Angle Functions
  990
- Software Angle Generator
  990
- Hardware Angle Generator (HWAG)
  995
- Hardware Angle Generator/High End Timer Interface
  995
- N2HET Control Registers
  1017
- Global Configuration Register (HETGCR) [Offset = 00H]
  1017
- Global Configuration Register (HETGCR)
  1018
- Prescale Factor Register (HETPFR)
  1020
- N2HET Current Address Register (HETADDR)
  1021
- Offset Index Priority Level 1 Register (HETOFF1)
  1021
- N2HET Current Address (HETADDR)
  1021
- Offset Index Priority Level 2 Register (HETOFF2)
  1022
- Interrupt Enable Set Register (HETINTENAS)
  1023
- Interrupt Enable Clear Register (HETINTENAC)
  1023
- Exception Control Register 1 (HETEXC1)
  1024
- Exception Control Register 2 (HETEXC2)
  1025
- Interrupt Priority Register (HETPRY)
  1026
- Interrupt Flag Register (HETFLG)
  1026
- AND Share Control Register (HETAND)
  1027
- HR Share Control Register (HETHRSH)
  1028
- XOR Share Control Register (HETXOR)
  1029
- Request Enable Set Register (HETREQENS)
  1030
- Request Enable Clear Register (HETREQENC)
  1030
- Request Destination Select Register (HETREQDS)
  1031
- NHET Direction Register (HETDIR)
  1032
- N2HET Data Input Register (HETDIN)
  1033
- N2HET Data Output Register (HETDOUT)
  1033
- NHET Data Set Register (HETDSET)
  1034
- N2HET Data Clear Register (HETDCLR)
  1034
- N2HET Open Drain Register (HETPDR)
  1035
- N2HET Pull Disable Register (HETPULDIS)
  1035
- N2HET Pull Select Register (HETPSL)
  1036
- Parity Control Register (HETPCR)
  1037
- Parity Address Register (HETPAR)
  1038
- Parity Pin Register (HETPPR)
  1039
- Suppression Filter Preload Register (HETSFPRLD)
  1040
- Suppression Filter Enable Register (HETSFENA)
  1040
- Loop Back Pair Select Register (HETLBPSEL)
  1041
- Loop Back Pair Direction Register (HETLBPDIR)
  1042
- N2HET Pin Disable Register (HETPINDIS)
  1043
- HWAG Registers
  1044
- HWAG Pin Select Register (HWAPINSEL)
  1045
- HWAG Global Control Register 0 (HWAGCR0)
  1046
- HWAG Global Control Register 1 (HWAGCR1)
  1046
- HWAG Global Control Register 2 (HWAGCR2)
  1047
- HWAG Interrupt Enable Set Register (HWAENASET)
  1048
- HWAG Interrupt Enable Clear Register (HWAENACLR)
  1049
- HWAG Interrupt Level Set Register (HWALVLSET)
  1050
- HWAG Interrupt Level Clear Register (HWALVLCLR)
  1050
- HWAG Interrupt Flag Register (HWAFLG)
  1051
- HWAG Interrupt Offset Register 0 (HWAOFF0)
  1052
- HWAG Interrupt Offset Register 1 (HWAOFF1)
  1053
- HWAG Angle Value Register (HWAACNT)
  1054
- HWAG Previous Tooth Period Value Register (HWAPCNT1)
  1055
- HWAG Current Tooth Period Value Register (HWAPCNT)
  1055
- HWAG Step Width Register (HWASTWD)
  1056
- HWAG Teeth Number Register (HWATHNB)
  1057
- HWAG Current Teeth Number Register (HWATHVL)
  1057
- HWAG Filter Register (HWAFIL)
  1058
- HWAG Filter Register 2 (HWAFIL2)
  1058
- HWAG Angle Increment Register (HWAANGI)
  1059
- Instruction Set
  1060
- Instruction Summary
  1060
- Abbreviations, Encoding Formats and Bits
  1062
- Instruction Description
  1065
- High-End Timer Transfer Unit (HTU) Module
  1131
24 High-End Timer Transfer Unit (HTU) Module

1132
25 General-Purpose Input/Output (GIO) Module

1184
- Overview
  1184
- Quick Start Guide
  1185
- Functional Description of GIO Module
  1187
- I/O Functions
  1187
- Interrupt Function
  1188
- GIO Block Diagram
  1188
- Device Modes of Operation
  1190
- Emulation Mode
  1190
- Power-Down Mode (Low-Power Mode)
  1190
- GIO Control Registers
  1191
- GIO Global Control Register (GIOGCR0)
  1192
- GIO Interrupt Detect Register (GIOINTDET)
  1193
- GIO Interrupt Polarity Register (GIOPOL)
  1194
- GIO Interrupt Enable Registers (GIOENASET and GIOENACLR)
  1195
- GIO Interrupt Priority Registers (GIOLVLSET and GIOLVLCLR)
  1197
- GIO Interrupt Flag Register (GIOFLG)
  1200
- GIO Offset Register 1 (GIOOFF1)
  1201
- GIO Offset B Register (GIOOFF2)
  1202
- GIO Emulation a Register (GIOEMU1)
  1203
- GIO Emulation B Register (GIOEMU2)
  1204
- GIO Data Direction Registers (GIODIR[A-B])
  1205
- GIO Data Input Registers (GIODIN[A-B])
  1205
- GIO Data Output Registers (GIODOUT[A-B])
  1206
- GIO Data Set Registers (GIODSET[A-B])
  1206
- GIO Data Clear Registers (GIODCLR[A-B])
  1207
- GIO Open Drain Registers (GIOPDR[A-B])
  1207
- GIO Pull Disable Registers (GIOPULDIS[A-B])
  1208
- GIO Pull Select Registers (GIOPSL[A-B])
  1208
- I/O Control Summary
  1209
- Flexray Module
  1210
26 Flexray Module

1211
- Overview
  1211
- Feature List
  1211
- Flexray Module Block Diagram
  1211
- Flexray Module Blocks
  1214
- Module Operation
  1215
- Transfer Unit
  1215
- Communication Cycle
  1226
- Communication Modes
  1227
- Clock Synchronization
  1228
- Error Handling
  1229
- Communication Controller States
  1231
- Network Management
  1243
- Filtering and Masking
  1243
- Transmit Process
  1246
- Receive Process
  1248
- FIFO Function
  1249
- Message Handling
  1250
- Module Rams
  1258
- Interrupts
  1269
- Minimum Peripheral Clock Frequency
  1274
- Assignment of Flexray Configuration Parameters
  1275
- Emulation/Debug Support
  1276
- Flexray Module Registers
  1277
- Transfer Unit Registers
  1277
- Communication Controller Registers
  1325
- Controller Area Network (DCAN) Module
  1417
27 Controller Area Network (DCAN) Module

1418

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Texas Instruments TMS570LC4357 Manuals

Texas Instruments TMS570LC4357 Technical Reference Manual (2208 pages)

Table of Contents

Preface

1 Introduction

2 Architecture

3 SCR Control Module (SCM)

4 Interconnect

5 Power Management Module (PMM)

6 I/O Multiplexing and Control Module (IOMM)

7 F021 Level 2 Flash Module Controller (L2FMC)

8 Level 2 RAM (L2RAMW) Module

9 Programmable Built-In Self-Test (PBIST) Module

10 Self-Test Controller (STC) Module

11 System Memory Protection Unit (NMPU)

12 Error Profiling Controller (EPC)

13 CPU Compare Module for Cortex-R5F (CCM-R5F)

14 Oscillator and PLL

15 Dual-Clock Comparator (DCC) Module

16 Error Signaling Module (ESM)

17 Real-Time Interrupt (RTI) Module

21 External Memory Interface (EMIF)

22 Analog to Digital Converter (ADC) Module

23 High-End Timer (N2HET) Module

24 High-End Timer Transfer Unit (HTU) Module

25 General-Purpose Input/Output (GIO) Module

26 Flexray Module

27 Controller Area Network (DCAN) Module

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