Serirq Control Register 1 (Sirqcr1) - Renesas H8S/2100 Series Hardware Manual

20.3.14 SERIRQ Control Register 1 (SIRQCR1)

SIRQCR1 contains status bits that indicate the SERIRQ operating mode and bits that specify
SERIRQ interrupt sources.
Bit Bit Name Initial Value Slave Host Description
7 IRQ11E3 0
6 IRQ10E3 0
R/W

Host IRQ11 Interrupt Enable 3
R/W
Enables or disables an HIRQ11 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ11 interrupt request by OBF3A and
IRQE11E3 is disabled
[Clearing conditions]
•
Writing 0 to IRQ11E3
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ11 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR3 = 1]
HIRQ11 interrupt is requested
[Setting condition]
Writing 1 after reading IRQ11E3 = 0

Host IRQ10 Interrupt Enable 3
R/W
Enables or disables an HIRQ10 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ10 interrupt request by OBF3A and
IRQE10E3 is disabled
[Clearing conditions]
•
Writing 0 to IRQ10E3
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ10 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR3 = 1]
HIRQ10 interrupt is requested
[Setting condition]
Writing 1 after reading IRQ10E3 = 0
Section 20 LPC Interface (LPC)
Rev. 1.00 Apr. 28, 2008 Page 649 of 994
REJ09B0452-0100