Data Cache Pins - Renesas NU85E Preliminary User's Manual

(13) IIRCAN (output)
This is the pin from which the code cancel status is output to the instruction cache.
This signal cancels previous requests when data becomes unwanted due to a branch or interrupt after the
NU85E outputs a fetch request to the instruction cache.
(14) BCUNCH (output)
This is the pin from which the uncache status is output to the instruction cache.
A low level is output when the area in which the instruction cache setting has been set to cache-enable using the
cache configuration register (BHC) is accessed.
(15) IBBTFT (input)
This is an NEC reserved pin. Always input a low level.
Note that the IBBTFT pin of the connected instruction cache should be left open when using the instruction
cache.

2.2.9 Data cache pins

(1) IDDARQ (output)
This is the pin from which read/write access requests are output to the data cache.
(2) IDAACK (output)
This is the pin from which acknowledgements are output to the data cache.
This signal is output when the NU85E recognizes the IDEA27 to IDEA0 signals input from the data cache.
(3) IDDRRQ, IDDWRQ, IDSEQ4, IDSEQ2 (input)
These are the pins to which the operation type settings are input from the data cache.
IDDRRQ IDDWRQ
1
1
1
0
0
0
1
1
1
Other than above
Remark 0: low-level input 1: high-level input
CHAPTER 2 PIN FUNCTIONS
Table 2-7. IDDRRQ, IDDWRQ, IDSEQ4, and IDSEQ2 Signals
IDSEQ4 IDSEQ2
0 1 0
0 0 1
0 0 0
1 1 0
1 0 1
1 0 0
1 1 1
1 1 0
1 0 0
Preliminary User's Manual A14874EJ3V0UM
Operation Type
4-word sequential read
2-word sequential read
1-word read
4-word sequential write
2-word sequential write
1-word write
1-word write
1-halfword write
1-byte write
Setting prohibited
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