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M30245 Group
4.2 Data Access
4.2.1 Data Bus Width
If the voltage level input to the BYTE pin is "H", the external data bus width becomes 8 bits, and P1
through P1
(/D
7
15
If the voltage level input to the BYTE pin is "L", the external data bus width becomes 16 bits, and P0
through P0
(/D
), and P1
7
7
N o t e 1 : C a n b e s w i t c h e d t o I / O p o r t u s i n g t h e p o r t P 4
N o t e 2 : W h e n r e s e t , o n l y C S
I / O p o r t s c a n b e s w i t c h e d u s i n g t h e C S i o u t p u t e n a b l e b i t o f t h e c h i p s e l e c t c o n t r o l r e g i s t e r ( a d d r e s s 0 0 0 8
N o t e 3 : T h e f e a t u r e c a n b e s w i t c h e d u s i n g t h e R / W m o d e s e l e c t b i t o f p r o c e s s o r m o d e r e g i s t e r 0 ( a d d r e s s 0 0 0 4
Figure 4.2.1. Level of BYTE pin and external data bus width
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
) can be used as I/O ports (Figure 4.2.1).
(/D
) through P1
0
8
B u s w i d t h : 8 - b i t ( B Y T E = " H " )
M i c r o c o m p u t e r
P0
to P0
0
7
P1
to P1
0
7
P2
to P2
0
7
P3
to P3
0
7
P4
to P4
0
3
A d d r e s s b u s A
P4
to P4
4
7
C h i p s e l e c t C S 0 t o C S 3 ( N o t e 2 )
P5
to P5
0
2
R D , W R L , W R H / R D , B H E , W R ( N o t e 3 )
P5
to P5
3
7
B C L K , H L D A , H O L D , A L E , R D Y
B u s w i d t h : 1 6 - b i t ( B Y T E = " L " )
M i c r o c o m p u t e r
P0
to P0
0
7
P1
to P1
0
7
P2
to P2
0
7
P3
to P3
0
7
P4
to P4
0
3
A d d r e s s b u s A
P4
to P4
4
7
C h i p s e l e c t C S 0 t o C S 3 ( N o t e 2 )
P5
to P5
0
2
RD,WRL,WRH / RD,BHE,WR (Note 3)
P5
to P5
3
7
BCLK, HLDA, HOLD, ALE, RDY
o u t p u t s a c h i p s e l e c t s i g n a l . C S
0
page 331 of 354
(/D
) operate as a data bus (D
7
15
E x t e r n a l d e v i c e
D a t a b u s D
t o D
0
7
I / O p o r t
A d d r e s s b u s A
t o A 1
0
5
t o A
( N o t e 1 )
1 6
1 9
E x t e r n a l d e v i c e
D a t a b u s D
t o D
0
7
D a t a b u s D
t o D
8
1 5
A d d r e s s b u s A
t o A 1
0
5
t o A
( N o t e 1 )
1 6
1 9
t o P 4
f u n c t i o n s e l e c t b i t s o f p r o c e s s o r m o d e r e g i s t e r 0 ( a d d r e s s 0 0 0 4
0
3
t h r o u g h C S
b e c o m e i n p u t p o r t s .
1
3
4. External Buses
0
0
through D
) (Figure 4.2.1).
0
15
) .
1 6
) .
1 6
) .
1 6
(/D
)
8
(/D
)
0
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