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Bit
Bit Name
3
IRQ1SCB
2
IRQ1SCA
1
IRQ0SCB
0
IRQ0SCA
5.3.5
IRQ Status Register (ISR)
ISR is an IRQ7 to IRQ0 interrupt request flag register.
Bit
Bit Name
7
IRQ7F
6
IRQ6F
5
IRQ5F
4
IRQ4F
3
IRQ3F
2
IRQ2F
1
IRQ1F
0
IRQ0F
Note:
* Only 0 can be written, to clear the flag.
Rev. 1.00, 09/03, page 74 of 704
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial Value R/W
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
Description
IRQ1 Sense Control B
IRQ1 Sense Control A
00: Interrupt request generated at IRQ1 input low
level
01: Interrupt request generated at falling edge of
IRQ1 input
10: Interrupt request generated at rising edge of IRQ1
input
11: Interrupt request generated at both falling and
rising edges of IRQ1 input
IRQ0 Sense Control B
IRQ0 Sense Control A
00: Interrupt request generated at IRQ0 input low
level
01: Interrupt request generated at falling edge of
IRQ0 input
10: Interrupt request generated at rising edge of IRQ0
input
11: Interrupt request generated at both falling and
rising edges of IRQ0 input
Description
[Setting condition]
•
When the interrupt source selected by ISCR
occurs
[Clearing conditions]
•
Cleared after reading condition1, when written as
0
•
When interrupt exception handling is executed
when low-level detection is set and IRQn input is
high
•
When IRQn interrupt exception handling is
executed while detecting the falling edge, rising
edge, or both
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