Srom Controller - Samsung S5PV210 Hardware Design Manual

S5PV210_HARDWARE DESING GUIDE REV 1.0

6. SROM Controller

6.1. Signal Description
Signal
SROM_CSn[5:0]
EBI_OEn
EBI_WEn
EBI_BEn[1:0]
SROM_WAITn
EBI_DATA_RDn
EBI_ADDR[15:0]
EBI_DATA[15:0]
Addr.
connection
16bit data
bus
1) SROM_BW [AddrMode] : Register for Address base of each memory bank
Note.
2) Bank0 supports only 16bit data bus width.
I/O Description
SROM Chip select
O
Note) Bank0 supports only 16bit data bus width.
O Memory Port 0 SROM / OneNAND Output Enable
O Memory Port 0 SROM / OneNAND Write Enable
O Memory Port 0 SROM Byte Enable
I Memory Port 0 SROM nWait
Memory Port 0 SROM/OneNAND/CF
O If data is output, this signal goes to High.
If data is input, this signal goes to Low.
O Memory port 0 Address bus
IO Memory port 0 Data bus
8bit data bus
Half-word base(AddrMode =0)(default)
Byte base(AddrMode =1)
SRAM/ROM S5PV210
A0
Xm0ADDR0
A0
Xm0ADDR0
A0
Xm0ADDR1
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