Interrupt Controller; Overview - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

INTERRUPT CONTROLLER

9
INTERRUPT CONTROLLER

1 OVERVIEW

The interrupt controller in the S3C2416 receives the request from 53 interrupt sources. These interrupt sources
are provided by internal peripherals such as the DMA controller, the UART, IIC, and others. In these interrupt
sources, the UARTn and EINTn interrupts are 'OR'ed to the interrupt controller.
When receiving multiple interrupt requests from internal peripherals and external interrupt request pins, the
interrupt controller requests FIQ or IRQ interrupt of the ARM926EJ core after the arbitration procedure.
The arbitration procedure depends on the hardware priority logic and the result is written to the interrupt pending
register, which helps users notify which interrupt is generated out of various interrupt sources.
INTPND
Request sources
SUBSRCPND SUBMASK SRCPND MASK
(with sub -register)
Priority IRQ
Request sources
MODE
(without sub -register)
FIQ
Figure 9-1. Interrupt Process Diagram
10-1