Usb Phy Control Register (Phyctrl) - Samsung S3C2416 User Manual

SYSTEM CONTROLLER
8.9

USB PHY CONTROL REGISTER (PHYCTRL)

Register
PHYCTRL 0x4C00_0080
PHYCTRL
RESERVED
CLK_ON_OFF
CLK_SEL
EXT_CLK
INT_PLL_SEL
DOWNSTREAM_
PORT
2-38
Address R/W
R/W
Bit
[31:6] -
[5] Clock input on off control at pad input area
Should be use with EXT_CLK [2].
When Combination of [5],[2] bit is 2'b11 , could be off clock
input.
00 = Crystal Enable,
01 = Oscillator Enable,
11 = Crystal/Oscillator Disable(PAD Disable),
10 = reserved
[4:3] Reference Clock Frequency Select
00 = 48MHz
01 = Reserved
10 = 12MHz
11 = 24MHz
[2] Clock Select
0 = Crystal
1 = Oscillator
[1] Host 1.1 uses which PLL Clock (48MHz)
0 = use EPLL
(USBHOSTCLK should be 48MHz and The CLK_SEL[1:0]
must be set to 2'b00)
1 = use USB own Internal PLL Clock
[0] Downstream Port Select
0 = Device (Function) Mode
1 = Host Mode
Description
USB2.0 PHY Control Register
Description
S3C2416X RISC MICROPROCESSOR
Reset Value
0x0000_0000
Initial State
0
0
2'b00
0
0
0