Power Management; Power Mode State Diagram - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

6 POWER MANAGEMENT

The power management block controls the system clocks by software for the reduction of power consumption in
S3C2416. These schemes are related to PLL, clock control logic(ARMCLK, HCLK, PCLK) and wake-up signal.
S3C2416 has four power-down modes. The following section describes each power management mode.
Related registers are PWRMODE, PWRCFG and WKUPSTAT.
6.1

POWER MODE STATE DIAGRAM

Figure 2-10 shows that Power Saving mode state and Entering or Exiting condition. In general, the entering
conditions are set by the main CPU.
STA NDBYW FI
O ne of
w akeup
source
ID LE
Figure 2-10. Power Mode State Diagram
N orm al
(G eneral Clock
G ating M ode)
O ne of
w akeup
source
R eset
or
CM D
restricted
w akeup
evants.
SLEEP
SYSTEM CONTROLLER
C M D
STO P
or D EEP-STO P
2-13