Operation; Figure 8.4 Flowchart Of Dtc Operation - Renesas H8S Series Hardware Manual

Section 8 Data Transfer Controller (DTC)
8.5

Operation

Register information is stored in on-chip memory. When activated, the DTC reads register
information in on-chip memory and transfers data. After the data transfer, the DTC writes updated
register information back to the memory.
The pre-storage of register information in memory makes it possible to transfer data over any
required number of channels. The transfer mode can be specified as normal, repeat, and block
transfer mode. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of
transfers with a single activation source (chain transfer).
The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed depending on its register information.
Rev. 6.00 Mar 15, 2006 page 114 of 570
REJ09B0211-0600
Start
Read DTC vector
Read register information
Data transfer
Write register information
CHNE = 1
Yes
No
Transfer Counter = 0
Yes
or DISEL = 1
No
Clear an activation flag
End

Figure 8.4 Flowchart of DTC Operation

Next transfer
Clear DTCER
Interrupt exception
handling