Control Signals Output By Bus Master - Renesas NU85E Preliminary User's Manual

4.9.2 Control signals output by bus master

When the NU85E operates as the bus master, the contents of the transfer that is currently being executed are
indicated by outputting the various control signals indicated below (When the NU85E operates as a bus slave, the
external bus master performs output, and this data is input to the NU85E as the VSxxxx signal).
However, the VxWAIT, VxAHLD, and VxLAST signals are output by the bus slave and input by the bus master
(The signal names on the bus master side are VMWAIT, VMAHLD, and VMLAST, and the signal names on the bus
slave side are VSWAIT, VSAHLD, and VSLAST).
(1) Transfer type
When the transfer begins, the bus master outputs the VMTTYP1 and VMTTYP0 signals to indicate the transfer
type.
VMTTYP1 VMTTYP0
0
1
1
0
Remark 0: low-level 1: high-level
(2) Bus cycle type
The bus master indicates the current bus cycle status according to the VMCTYP2 to VMCTYP0 signals.
VMCTYP2 VMCTYP1
0
0
0
0
1
1
1
1
Note Output only when a high level is input to the IFIMAEN pin (misalign access enabled).
Remark 0: low-level 1: high-level
CHAPTER 4 BCU
Table 4-1. VMTTYP1 and VMTTYP0 Signals
0 Address-only transfer (transfer without data processing)
0 Non-sequential transfer (single transfer or burst transfer)
1 Sequential transfer (transfer in which the address currently being
transferred is related to the previously transferred address)
1 (Reserved for future function expansion)
Table 4-2. VMCTYP2 to VMCTYP0 Signals
VMCTYP0
0 0 Opcode fetch
0 1 Data access
1 0 Misalign access
1 1 Read modify write access
0 0 Opcode fetch of jump address due to branch instruction
1 0 DMA 2-cycle transfer
1 1 DMA flyby transfer
0 1 (Reserved for future function expansion)
Preliminary User's Manual A14874EJ3V0UM
Transfer Type
Bus Cycle Status
Note
95