Figure 6.53 Example Of Idle Cycle Operation After Dram Write Access (Idlc = 0, Icis1 = 0, Rast = 0, Cast = 0) - Renesas H8S/2368 Series Hardware Manual

• Normal space access after DRAM space write access
While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space
write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to
be inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit
in DRACCR. Figure 6.53 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
Note: The DRAM interface is not supported by the H8S/2366.
DRAM space read External space read DRAM space read
T T T T T T T T T T
p r c1 c2 i 1 2 3 c1 c2
Address bus
,
,
Data bus
Idle cycle
Figure 6.53 Example of Idle Cycle Operation after DRAM Write Access
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)
Rev. 2.00, 05/03, page 186 of 820