Figure 7.29 Example Of Single Address Mode Transfer (Word Write) - Renesas H8S/2368 Series Hardware Manual

Address bus
Bus
release

Figure 7.29 Example of Single Address Mode Transfer (Word Write)

A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel DREQ DREQ DREQ
for which the DREQ pin is selected.
Figure 7.30 shows an example of single address mode transfer activated by the DREQ pin falling
edge.
Rev. 2.00, 05/03, page 260 of 820
DMA write
Bus
release
DMA write
Bus
release
DMA
DMA write dead
Last transfer Bus
cycle release